40. MICRO 2007: Chicago, Illinois, USA

40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 1-5 December 2007, Chicago, Illinois, USA. IEEE Computer Society 2007 BibTeX

Technology Issues

Naveen Muralimanohar, Rajeev Balasubramonian, Norman P. Jouppi:
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0. 3-14
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Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Brooks:
Process Variation Tolerant 3T1D-Based Cache Architectures. 15-26
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Radu Teodorescu, Jun Nakano, Abhishek Tiwari, Josep Torrellas:
Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing. 27-42
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Instruction Scheduling

Sebastian Winkel:
Optimal versus Heuristic Global Code Scheduling. 43-55
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Guilherme Ottoni, David I. August:
Global Multi-Threaded Instruction Scheduling. 56-68
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Matthew J. Bridges, Neil Vachharajani, Yun Zhang, Thomas Jablin, David I. August:
Revisiting the Sequential Programming Model for Multi-Core. 69-84
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Wear-Out Aware Architectures

Jaume Abella, Xavier Vera, Antonio González:
Penelope: The NBTI-Aware Processor. 85-96
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Kypros Constantinides, Onur Mutlu, Todd M. Austin, Valeria Bertacco:
Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation. 97-108
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Jason A. Blome, Shuguang Feng, Shantanu Gupta, Scott A. Mahlke:
Self-calibrating Online Wearout Detection. 109-122
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Memory

Daniel Sanchez, Luke Yen, Mark D. Hill, Karthikeyan Sankaralingam:
Implementing Signatures for Transactional Memory. 123-133
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Mrinmoy Ghosh, Hsien-Hsin S. Lee:
Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs. 134-145
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Onur Mutlu, Thomas Moscibroda:
Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors. 146-160
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Networking and Security

Amit Kumar, Ram Huggahalli:
Impact of Cache Coherence Protocols on the Processing of Network Traffic. 161-171
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John Kim, James D. Balfour, William J. Dally:
Flattened Butterfly Topology for On-Chip Networks. 172-182
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Brian Rogers, Siddhartha Chhabra, Milos Prvulovic, Yan Solihin:
Using Address Independent Seed Encryption and Bonsai Merkle Trees to Make Secure Processors OS- and Performance-Friendly. 183-196
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Reliability

Jangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Falsafi, James C. Hoe:
Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding. 197-209
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Albert Meixner, Michael E. Bauer, Daniel J. Sorin:
Argus: Low-Cost, Comprehensive Error Detection in Simple Cores. 210-222
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Niti Madan, Rajeev Balasubramonian:
Leveraging 3D Technology for Improved Reliability. 223-235
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Francisco J. Mesa-Martinez, Jose Renau:
Effective Optimistic-Checker Tandem Core Design through Architectural Pruning. 236-248
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Simulation/Workload Analysis

Derek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil A. Patil, William H. Reinhart, Darrel Eric Johnson, Jebediah Keefe, Hari Angepat:
FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators. 249-261
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Christophe Dubach, Timothy M. Jones, Michael F. P. O'Boyle:
Microarchitectural Design Space Exploration Using an Architecture-Centric Approach. 262-271
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Chang-Burm Cho, Wangyuan Zhang, Tao Li:
Informed Microarchitecture Design Space Exploration Using Workload Dynamics. 274-285
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Todd Mytkowicz, Peter F. Sweeney, Matthias Hauswirth, Amer Diwan:
Time Interpolation: So Many Metrics, So Few Registers. 286-300
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Prefetching and Snooping

Yuan Chou:
Low-Cost Epoch-Based Correlation Prefetching for Commercial Applications. 301-313
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Jason Zebchuk, Elham Safi, Andreas Moshovos:
A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy. 314-327
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Karin Strauss, Xiaowei Shen, Josep Torrellas:
Uncorq: Unconstrained Snoop Request Delivery in Embedded-Ring Multiprocessors. 327-342
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Parallelism and QoS in CMPs

Fei Guo, Yan Solihin, Li Zhao, Ravishankar Iyer:
A Framework for Providing Quality of Service in Chip Multi-Processors. 343-355
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William Thies, Vikram Chandrasekhar, Saman P. Amarasinghe:
A Practical Approach to Exploiting Coarse-Grained Pipeline Parallelism in C Programs. 356-369
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Michael L. Chu, Rajiv A. Ravindran, Scott A. Mahlke:
Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures. 369-380
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Parallel Architectures

Changkyu Kim, Simha Sethumadhavan, M. S. Govindan, Nitya Ranganathan, Divya Gulati, Doug Burger, Stephen W. Keckler:
Composable Lightweight Processors. 381-394
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Thomas Y. Yeh, Petros Faloutsos, Milos Ercegovac, Sanjay J. Patel, Glenn Reinman:
The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration. 394-406
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Wilson W. L. Fung, Ivan Sham, George Yuan, Tor M. Aamodt:
Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow. 407-420
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Cache Replacement Policies

Arkaprava Basu, Nevin Kirman, Meyrem Kirman, Mainak Chaudhuri, José F. Martínez:
Scavenger: A New Last Level Cache Architecture with Global Block Priority. 421-432
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Stephen Hines, David B. Whalley, Gary S. Tyson:
Guaranteeing Hits to Improve the Efficiency of a Small Instruction Cache. 433-444
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Kaushik Rajan, Govindarajan Ramaswamy:
Emulating Optimal Replacement with a Shepherd Cache. 445-454
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