Okihiko Ishizuka

2005
19	EE	Koichi Tanno, Kiminobu Sato, Hisashi Tanaka, Okihiko Ishizuka: Low-Voltage, Low-Distortion and Rail-to-Rail CMOS Sample and Hold Circuit. IEICE Transactions 88-A(10): 2696-2698 (2005)
18	EE	Koichi Tanno, Kenya Kondo, Okihiko Ishizuka, Takako Toyama: Combiner-Based MOS OTAs. IEICE Transactions 88-A(6): 1622-1625 (2005)
2002
17	EE	Motoi Inaba, Koichi Tanno, Okihiko Ishizuka: Multi-Valued Flip-Flop with Neuron-CMOS NMIN Circuits. ISMVL 2002: 282-
2001
16		Motoi Inaba, Koichi Tanno, Okihiko Ishizuka: Realization of NMAX and NMIN Functions with Multi-Valued Voltage Comparators. ISMVL 2001: 27-
15	EE	Koichi Tashima, Zheng Tang, Okihiko Ishizuka, Koichi Tanno: An immune network with interactions between B cells for pattern recognition. Systems and Computers in Japan 32(10): 31-41 (2001)
2000
14	EE	Jing Shen, Motoi Inaba, Koichi Tanno, Okihiko Ishizuka: Multi-Valued Logic Pass Gate Network Using Neuron-MOS Transistors. ISMVL 2000: 15-20
13	EE	Makoto Syuto, Jing Shen, Koichi Tanno, Okihiko Ishizuka: Multi-Input Variable-Threshold Circuits for Multi-Valued Logic Functions. ISMVL 2000: 27-32
1999
12	EE	Jing Shen, Koichi Tanno, Okihiko Ishizuka: Down Literal Circuit with Neuron-MOS Transistors and Its Applications. ISMVL 1999: 180-185
1998
11	EE	Jing Shen, Koichi Tanno, Okihiko Ishizuka, Zheng Tang: Application of Neuron-MOS to Current-Mode Multi-Valued Logic Circuits. ISMVL 1998: 128-133
10		Zheng Tang, Okihiko Ishizuka: A Learning Multiple-Valued Logic Network: Algebra, Algorithm, and Applications. IEEE Trans. Computers 47(2): 247-251 (1998)
1997
9	EE	Okihiko Ishizuka, Akihiro Ohta, Koichi Tanno, Zheng Tang, Dwi Handoko: VLSI Design of a Quaternary Multiplier with Direct Generation of Partial Products. ISMVL 1997: 169-174
8	EE	Zheng Tang, T. Yamaguchi, Koichi Tashima, Okihiko Ishizuka, Koichi Tanno: Multiple-Valued Immune Network Model and Its Simulations. ISMVL 1997: 233-
1995
7		Zheng Tang, Yuichi Shirata, Okihiko Ishizuka, Koichi Tanno: A Self-Calibrating A/D Converter Using T-Model Neural Network. ISCAS 1995: 533-536
6	EE	Zheng Tang, Okihiko Ishizuka, Koichi Tanno: Learning Multiple-Valued Logic Networks Based on Back Propagation. ISMVL 1995: 270-275
1993
5		Zheng Tang, Okihiko Ishizuka, Qi-xin Cao, Hiroki Matsumoto: Algebraic Properties of a Learning Multiple-Valued Logic Network. ISMVL 1993: 196-201
4		Qi-xin Cao, Okihiko Ishizuka, Zheng Tang, Hiroki Matsumoto: Algorithm and Implementation of a Learning Multiple-Valued Logic Network. ISMVL 1993: 202-207
1991
3		Okihiko Ishizuka, Hiroshi Takarabe, Zheng Tang, Hiroki Matsumoto: Synthesis of Current-Mode Pass Transistor Networks. ISMVL 1991: 139-146
1990
2		Okihiko Ishizuka, Zheng Tang, Hiroki Matsumoto: On Design of Multiple-Valued Static Random-Access-Memory. ISMVL 1990: 11-17
1977
1		Okihiko Ishizuka: On Multivalued Multithreshold Networks Composed of Conventional Threshold Elements. IEEE Trans. Computers 26(12): 1251-1257 (1977)

Coauthor Index

1	Qi-xin Cao	[4] [5]
2	Dwi Handoko	[9]
3	Motoi Inaba	[14] [16] [17]
4	Kenya Kondo	[18]
5	Hiroki Matsumoto	[2] [3] [4] [5]
6	Akihiro Ohta	[9]
7	Kiminobu Sato	[19]
8	Jing Shen	[11] [12] [13] [14]
9	Yuichi Shirata	[7]
10	Makoto Syuto	[13]
11	Hiroshi Takarabe	[3]
12	Hisashi Tanaka	[19]
13	Zheng Tang	[2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [15]
14	Koichi Tanno	[6] [7] [8] [9] [11] [12] [13] [14] [15] [16] [17] [18] [19]
15	Koichi Tashima	[8] [15]
16	Takako Toyama	[18]
17	T. Yamaguchi	[8]