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Koichi Tanno

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2008
16EEHiroki Tamura, Koichi Tanno: Midpoint-Validation Method for Support Vector Machine Classification. IEICE Transactions 91-D(7): 2095-2098 (2008)
2006
15EEMuneo Kushima, Motoi Inaba, Koichi Tanno: Linear and Compact Floating Node Voltage-Controlled Variable Resistor Circuit. IEICE Transactions 89-A(2): 459-460 (2006)
2005
14EEKoichi Tanno, Kiminobu Sato, Hisashi Tanaka, Okihiko Ishizuka: Low-Voltage, Low-Distortion and Rail-to-Rail CMOS Sample and Hold Circuit. IEICE Transactions 88-A(10): 2696-2698 (2005)
13EEKoichi Tanno, Kenya Kondo, Okihiko Ishizuka, Takako Toyama: Combiner-Based MOS OTAs. IEICE Transactions 88-A(6): 1622-1625 (2005)
2002
12EEMotoi Inaba, Koichi Tanno, Okihiko Ishizuka: Multi-Valued Flip-Flop with Neuron-CMOS NMIN Circuits. ISMVL 2002: 282-
2001
11 Motoi Inaba, Koichi Tanno, Okihiko Ishizuka: Realization of NMAX and NMIN Functions with Multi-Valued Voltage Comparators. ISMVL 2001: 27-
10EEKoichi Tashima, Zheng Tang, Okihiko Ishizuka, Koichi Tanno: An immune network with interactions between B cells for pattern recognition. Systems and Computers in Japan 32(10): 31-41 (2001)
2000
9EEJing Shen, Motoi Inaba, Koichi Tanno, Okihiko Ishizuka: Multi-Valued Logic Pass Gate Network Using Neuron-MOS Transistors. ISMVL 2000: 15-20
8EEMakoto Syuto, Jing Shen, Koichi Tanno, Okihiko Ishizuka: Multi-Input Variable-Threshold Circuits for Multi-Valued Logic Functions. ISMVL 2000: 27-32
1999
7EEJing Shen, Koichi Tanno, Okihiko Ishizuka: Down Literal Circuit with Neuron-MOS Transistors and Its Applications. ISMVL 1999: 180-185
1998
6EEJing Shen, Koichi Tanno, Okihiko Ishizuka, Zheng Tang: Application of Neuron-MOS to Current-Mode Multi-Valued Logic Circuits. ISMVL 1998: 128-133
1997
5EEOkihiko Ishizuka, Akihiro Ohta, Koichi Tanno, Zheng Tang, Dwi Handoko: VLSI Design of a Quaternary Multiplier with Direct Generation of Partial Products. ISMVL 1997: 169-174
4EEZheng Tang, T. Yamaguchi, Koichi Tashima, Okihiko Ishizuka, Koichi Tanno: Multiple-Valued Immune Network Model and Its Simulations. ISMVL 1997: 233-
1995
3EEKoichi Tanno, Akio Koyama, T. Taketa, Shoichi Noguchi: Buffer insertion/self-token (BIST) protocol for multimedia LANs. ICNP 1995: 350-355
2 Zheng Tang, Yuichi Shirata, Okihiko Ishizuka, Koichi Tanno: A Self-Calibrating A/D Converter Using T-Model Neural Network. ISCAS 1995: 533-536
1EEZheng Tang, Okihiko Ishizuka, Koichi Tanno: Learning Multiple-Valued Logic Networks Based on Back Propagation. ISMVL 1995: 270-275

Coauthor Index

1Dwi Handoko [5]
2Motoi Inaba [9] [11] [12] [15]
3Okihiko Ishizuka [1] [2] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14]
4Kenya Kondo [13]
5Akio Koyama [3]
6Muneo Kushima [15]
7Shoichi Noguchi [3]
8Akihiro Ohta [5]
9Kiminobu Sato [14]
10Jing Shen [6] [7] [8] [9]
11Yuichi Shirata [2]
12Makoto Syuto [8]
13T. Taketa [3]
14Hiroki Tamura [16]
15Hisashi Tanaka [14]
16Zheng Tang [1] [2] [4] [5] [6] [10]
17Koichi Tashima [4] [10]
18Takako Toyama [13]
19T. Yamaguchi [4]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)