| 1995 |
|---|
| 5 | EE | Mike Simone,
A. Essen,
A. Ike,
A. Krishnamoorthy,
Tak Maruyama,
Niteen Patkar,
M. Ramaswami,
Michael Shebanow,
V. Thirumalaiswamy,
DeForest Tovey:
Implementation Trade-Offs in Using a Restricted Data Flow Architecture in a High Performance RISC Microprocessor.
ISCA 1995: 151-162 |
| 1991 |
|---|
| 4 | EE | Michael Butler,
Tse-Yu Yeh,
Yale N. Patt,
Mitch Alsup,
Hunter Scales,
Michael Shebanow:
Single Instruction Stream Parallelism is Greater Than Two.
ISCA 1991: 276-286 |
| 1988 |
|---|
| 3 | EE | Stephen W. Melvin,
Michael Shebanow,
Yale N. Patt:
Hardware support for large atomic units in dynamically scheduled machines.
MICRO 1988: 60-63 |
| 1987 |
|---|
| 2 | EE | James E. Wilson,
Stephen W. Melvin,
Michael Shebanow,
Wen-mei W. Hwu,
Yale N. Patt:
On tuning the microarchitecture of an HPS implementation of the VAX.
MICRO 1987: 162-167 |
| 1986 |
|---|
| 1 | | Yale N. Patt,
Wen-mei W. Hwu,
Stephen W. Melvin,
Michael Shebanow,
Chein Chen,
Jiajuin Wei:
Experiments with HPS, a Restricted Data Flow Microarchitecture for High Performance Computers.
COMPCON 1986: 254-258 |
