Michael Shebanow

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5EEMike Simone, A. Essen, A. Ike, A. Krishnamoorthy, Tak Maruyama, Niteen Patkar, M. Ramaswami, Michael Shebanow, V. Thirumalaiswamy, DeForest Tovey: Implementation Trade-Offs in Using a Restricted Data Flow Architecture in a High Performance RISC Microprocessor. ISCA 1995: 151-162
4EEMichael Butler, Tse-Yu Yeh, Yale N. Patt, Mitch Alsup, Hunter Scales, Michael Shebanow: Single Instruction Stream Parallelism is Greater Than Two. ISCA 1991: 276-286
3EEStephen W. Melvin, Michael Shebanow, Yale N. Patt: Hardware support for large atomic units in dynamically scheduled machines. MICRO 1988: 60-63
2EEJames E. Wilson, Stephen W. Melvin, Michael Shebanow, Wen-mei W. Hwu, Yale N. Patt: On tuning the microarchitecture of an HPS implementation of the VAX. MICRO 1987: 162-167
1 Yale N. Patt, Wen-mei W. Hwu, Stephen W. Melvin, Michael Shebanow, Chein Chen, Jiajuin Wei: Experiments with HPS, a Restricted Data Flow Microarchitecture for High Performance Computers. COMPCON 1986: 254-258

Coauthor Index

1Mitch Alsup [4]
2Michael Butler [4]
3Chein Chen [1]
4A. Essen [5]
5Wen-mei W. Hwu [1] [2]
6A. Ike [5]
7A. Krishnamoorthy [5]
8Tak Maruyama [5]
9Stephen W. Melvin [1] [2] [3]
10Niteen Patkar [5]
11Yale N. Patt [1] [2] [3] [4]
12M. Ramaswami [5]
13Hunter Scales [4]
14Mike Simone [5]
15V. Thirumalaiswamy [5]
16DeForest Tovey [5]
17Jiajuin Wei [1]
18James E. Wilson [2]
19Tse-Yu Yeh [4]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)