| 2007 |
|---|
| 8 | EE | Jeegar Tilak Shah,
Marius Evers,
Jeff Trull,
Alper Halbutogullari:
Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors.
ISPD 2007: 67-74 |
| 1998 |
|---|
| 7 | EE | Jared Stark,
Marius Evers,
Yale N. Patt:
Variable Length Path Branch Prediction.
ASPLOS 1998: 170-179 |
| 6 | EE | Sanjay J. Patel,
Marius Evers,
Yale N. Patt:
Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing.
ISCA 1998: 262-271 |
| 5 | EE | Marius Evers,
Sanjay J. Patel,
Robert S. Chappell,
Yale N. Patt:
An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work.
ISCA 1998: 52-61 |
| 4 | | Eric Hao,
Po-Yung Chang,
Marius Evers,
Yale N. Patt:
Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures.
International Journal of Parallel Programming 26(4): 449-478 (1998) |
| 1997 |
|---|
| 3 | | Yale N. Patt,
Sanjay J. Patel,
Marius Evers,
Daniel H. Friendly,
Jared Stark:
One Billion Transistors, One Uniprocessor, One Chip.
IEEE Computer 30(9): 51-57 (1997) |
| 1996 |
|---|
| 2 | EE | Marius Evers,
Po-Yung Chang,
Yale N. Patt:
Using Hybrid Branch Predictors to Improve Branch Prediction Accuracy in the Presence of Context Switches.
ISCA 1996: 3-11 |
| 1 | EE | Eric Hao,
Po-Yung Chang,
Marius Evers,
Yale N. Patt:
Increasing the Instruction Fetch Rate via Block-structured Instruction Set Architectures.
MICRO 1996: 191-200 |
