Marius Evers

List of publications from the DBLP Bibliography Server - FAQ
Coauthor Index - Ask others: ACM DL/Guide - CiteSeer - CSB - Google - MSN - Yahoo

8EEJeegar Tilak Shah, Marius Evers, Jeff Trull, Alper Halbutogullari: Circuit optimization for leakage power reduction using multi-threshold voltages for high performance microprocessors. ISPD 2007: 67-74
7EEJared Stark, Marius Evers, Yale N. Patt: Variable Length Path Branch Prediction. ASPLOS 1998: 170-179
6EESanjay J. Patel, Marius Evers, Yale N. Patt: Improving Trace Cache Effectiveness with Branch Promotion and Trace Packing. ISCA 1998: 262-271
5EEMarius Evers, Sanjay J. Patel, Robert S. Chappell, Yale N. Patt: An Analysis of Correlation and Predictability: What Makes Two-Level Branch Predictors Work. ISCA 1998: 52-61
4 Eric Hao, Po-Yung Chang, Marius Evers, Yale N. Patt: Increasing the Instruction Fetch Rate via Block-Structured Instruction Set Architectures. International Journal of Parallel Programming 26(4): 449-478 (1998)
3 Yale N. Patt, Sanjay J. Patel, Marius Evers, Daniel H. Friendly, Jared Stark: One Billion Transistors, One Uniprocessor, One Chip. IEEE Computer 30(9): 51-57 (1997)
2EEMarius Evers, Po-Yung Chang, Yale N. Patt: Using Hybrid Branch Predictors to Improve Branch Prediction Accuracy in the Presence of Context Switches. ISCA 1996: 3-11
1EEEric Hao, Po-Yung Chang, Marius Evers, Yale N. Patt: Increasing the Instruction Fetch Rate via Block-structured Instruction Set Architectures. MICRO 1996: 191-200

Coauthor Index

1Po-Yung Chang [1] [2] [4]
2Robert S. Chappell [5]
3Daniel H. Friendly [3]
4Alper Halbutogullari [8]
5Eric Hao [1] [4]
6Sanjay J. Patel [3] [5] [6]
7Yale N. Patt [1] [2] [3] [4] [5] [6] [7]
8Jeegar Tilak Shah [8]
9Jared Stark [3] [7]
10Jeff Trull [8]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)