| 2007 |
|---|
| 3 | EE | Ivo Koren,
Frank Demmerle,
Roland May,
Martin Kaibel,
Sebastian Sattler:
FPGA Architecture for RF Transceiver System and Mixed-Signal Low Cost Tests.
European Test Symposium 2007: 43-48 |
| 2 | EE | Matthias Beck,
Olivier Barondeau,
Martin Kaibel,
Frank Poehl,
Xijiang Lin,
Ron Press:
Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality
CoRR abs/0710.4763: (2007) |
| 2005 |
|---|
| 1 | EE | Matthias Beck,
Olivier Barondeau,
Martin Kaibel,
Frank Poehl,
Xijiang Lin,
Ron Press:
Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality.
DATE 2005: 56-61 |
