2000 |
20 | EE | Jay Bharadwaj,
William Y. Chen,
Weihaw Chuang,
Gerolf Hoflehner,
Kishore N. Menezes,
Kalyan Muthukumar,
Jim Pierce:
The Intel IA-64 Compiler Code Generator.
IEEE Micro 20(5): 44-53 (2000) |
1998 |
19 | EE | Pohua P. Chang,
Scott A. Mahlke,
William Y. Chen,
Nancy J. Warter,
Wen-mei W. Hwu:
IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors.
25 Years ISCA: Retrospectives and Reprints 1998: 408-417 |
1995 |
18 | | Pohua P. Chang,
Daniel M. Lavery,
Scott A. Mahlke,
William Y. Chen,
Wen-mei W. Hwu:
The Importance of Prepass Code Scheduling for Superscalar and Superpipelined Processors.
IEEE Trans. Computers 44(3): 353-370 (1995) |
17 | | Pohua P. Chang,
Nancy J. Warter,
Scott A. Mahlke,
William Y. Chen,
Wen-mei W. Hwu:
Three Architecutral Models for Compiler-Controlled Speculative Execution.
IEEE Trans. Computers 44(4): 481-494 (1995) |
1994 |
16 | | David M. Gallagher,
William Y. Chen,
Scott A. Mahlke,
John C. Gyllenhaal,
Wen-mei W. Hwu:
Dynamic Memory Disambiguation Using the Memory Conflict Buffer.
ASPLOS 1994: 183-193 |
1993 |
15 | | Tokuzo Kiyohara,
Scott A. Mahlke,
William Y. Chen,
Roger A. Bringmann,
Richard E. Hank,
Sadun Anik,
Wen-mei W. Hwu:
Register Connection: A New Approach to Adding Registers into Instruction Set Architectures.
ISCA 1993: 247-256 |
14 | EE | Scott A. Mahlke,
William Y. Chen,
Roger A. Bringmann,
Richard E. Hank,
Wen-mei W. Hwu,
B. Ramakrishna Rau,
Michael S. Schlansker:
Sentinel Scheduling for VLIW and Superscalar Processors.
ACM Trans. Comput. Syst. 11(4): 376-408 (1993) |
13 | | William Y. Chen,
Pohua P. Chang,
Thomas M. Conte,
Wen-mei W. Hwu:
The Effect of Code Expanding Optimizations on Instruction Cache Design.
IEEE Trans. Computers 42(9): 1045-1057 (1993) |
1992 |
12 | | Scott A. Mahlke,
William Y. Chen,
Wen-mei W. Hwu,
B. Ramakrishna Rau,
Michael S. Schlansker:
Sentinel Scheduling for VLIW and Superscalar Processors.
ASPLOS 1992: 238-247 |
11 | | William Y. Chen,
Scott A. Mahlke,
Wen-mei W. Hwu:
Tolerating First Level Memory Access Latency in High-Performance Systems.
ICPP (1) 1992: 36-43 |
10 | EE | William Y. Chen,
Scott A. Mahlke,
Wen-mei W. Hwu,
Tokuzo Kiyohara,
Pohua P. Chang:
Tolerating data access latency with register preloading.
ICS 1992: 104-113 |
9 | | William Y. Chen,
Roger A. Bringmann,
Scott A. Mahlke,
Sadun Anik,
Tokuzo Kiyohara,
Nancy J. Warter,
Daniel M. Lavery,
Wen-mei W. Hwu,
Richard E. Hank,
John C. Gyllenhaal:
Using Profile Information to Assist Advaced Compiler Optimization and Scheduling.
LCPC 1992: 31-48 |
8 | EE | Scott A. Mahlke,
David C. Lin,
William Y. Chen,
Richard E. Hank,
Roger A. Bringmann:
Effective compiler support for predicated execution using the hyperblock.
MICRO 1992: 45-54 |
7 | EE | William Y. Chen,
Roger A. Bringmann,
Scott A. Mahlke,
Richard E. Hank,
James E. Sicolo:
An efficient architecture for loop based data preloading.
MICRO 1992: 92-101 |
6 | | Scott A. Mahlke,
William Y. Chen,
John C. Gyllenhaal,
Wen-mei W. Hwu:
Compiler Code Transformations for Superscalar-Based High Performance Systems.
SC 1992: 808-817 |
5 | | Pohua P. Chang,
Scott A. Mahlke,
William Y. Chen,
Wen-mei W. Hwu:
Profile-guided Automatic Inline Expansion for C Programs.
Softw., Pract. Exper. 22(5): 349-369 (1992) |
1991 |
4 | | Scott A. Mahlke,
Nancy J. Warter,
William Y. Chen,
Pohua P. Chang,
Wen-mei W. Hwu:
The Effect of Compiler Optimizations on Available Parallelism in Scalar Programs.
ICPP (2) 1991: 142-145 |
3 | EE | Pohua P. Chang,
Scott A. Mahlke,
William Y. Chen,
Nancy J. Warter,
Wen-mei W. Hwu:
IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors.
ISCA 1991: 266-275 |
2 | EE | Pohua P. Chang,
William Y. Chen,
Scott A. Mahlke,
Wen-mei W. Hwu:
Comparing Static and Dynamic Code Scheduling for Multiple-Instruction-Issue Processors.
MICRO 1991: 25-33 |
1 | EE | William Y. Chen,
Scott A. Mahlke,
Pohua P. Chang,
Wen-mei W. Hwu:
Data Access Microarchitectures for Superscalar Processors with Compiler-Assisted Data Prefetching.
MICRO 1991: 69-73 |