HiPEAC 2007: Ghent, Belgium

Koen De Bosschere, David R. Kaeli, Per Stenström, David B. Whalley, Theo Ungerer (Eds.): High Performance Embedded Architectures and Compilers, Second International Conference, HiPEAC 2007, Ghent, Belgium, January 28-30, 2007, Proceedings. Lecture Notes in Computer Science 4367 Springer 2007, ISBN 978-3-540-69337-6 BibTeX

Invited Program

Thomas M. Conte:
Keynote: Insight, Not (Random) Numbers: An Embedded Perspective. 3
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Vijay Nagarajan, Rajiv Gupta, Arvind Krishnaswamy:
Compiler-Assisted Memory Encryption for Embedded Processors. 7-22
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Major Bhadauria, Sally A. McKee, Karan Singh, Gary S. Tyson:
Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems. 23-37
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Georgios Keramidas, Polychronis Xekalakis, Stefanos Kaxiras:
Applying Decay to Reduce Dynamic Power in Set-Associative Caches. 38-53
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Jun Yan, Wei Zhang:
Virtual Registers: Reducing Register Pressure Without Enlarging the Register File. 57-70
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Weihaw Chuang, Satish Narayanasamy, Brad Calder, Ranjit Jhala:
Bounds Checking with Taint-Based Analysis. 71-86
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Apala Guha, Kim M. Hazelwood, Mary Lou Soffa:
Reducing Exit Stub Memory Consumption in Code Caches. 87-101
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Chang-Ching Yeh, Kuei-Chung Chang, Tien-Fu Chen, Chingwei Yeh:
Reducing Branch Misprediction Penalties Via Adaptive Pipeline Scaling. 105-119
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Hans Vandierendonck, André Seznec:
Fetch Gating Control Through Speculative Instruction Window Weighting. 120-135
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Sonia López, Steve Dropsho, David H. Albonesi, Oscar Garnica, Juan Lanchares:
Dynamic Capacity-Speed Tradeoffs in SMT Processor Caches. 136-150
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Simon Kluyskens, Lieven Eeckhout:
Branch History Matching: Branch Predictor Warmup for Sampled Simulation. 153-167
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Phillip Stanley-Marbell, Diana Marculescu:
Sunflower : Full-System, Embedded Microarchitecture Evaluation. 168-182
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Chunling Hu, Daniel A. Jiménez, Ulrich Kremer:
Efficient Program Power Behavior Characterization. 183-197
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Paolo D'Alberto, Markus Püschel, Franz Franchetti:
Performance/Energy Optimization of DSP Transforms on the XScale Processor. 201-214
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Klaas L. Hofstra, Sabih H. Gerez:
Arx: A Toolset for the Efficient Simulation and Direct Synthesis of High-Performance Signal Processing Algorithms. 215-226
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Lixia Liu, Xiao-Feng Li, Michael K. Chen, Roy Dz-Ching Ju:
A Throughput-Driven Task Creation and Mapping for Network Processors. 227-241
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Grigori Fursin, John Cavazos, Michael F. P. O'Boyle, Olivier Temam:
MiDataSets: Creating the Conditions for a More Realistic Evaluation of Iterative Optimization. 245-260
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Johnny Huynh, José Nelson Amaral, Paul Berube, Sid Ahmed Ali Touati:
Evaluation of Offset Assignment Heuristics. 261-275
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Mazen A. R. Saghir, Mohamad El-Majzoub, Patrick Akl:
Customizing the Datapath and ISA of Soft VLIW Processors. 276-290
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I-Wei Wu, Shih-Chia Huang, Chung-Ping Chung, Jean Jyh-Jiun Shann:
Instruction Set Extension Generation with Considering Physical Constraints. 291-305
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