| 2000 |
|---|
| 8 | EE | Vasanth Bala,
Evelyn Duesterwald,
Sanjeev Banerjia:
Dynamo: a transparent dynamic optimization system.
PLDI 2000: 1-12 |
| 1998 |
|---|
| 7 | EE | William A. Havanki,
Sanjeev Banerjia,
Thomas M. Conte:
Treegion Scheduling for Wide Issue Processors.
HPCA 1998: 266-276 |
| 6 | EE | Emre Özer,
Sumedh W. Sathaye,
Kishore N. Menezes,
Sanjeev Banerjia,
Matthew D. Jennings,
Thomas M. Conte:
A Fast Interrupt Handling Scheme for VLIW Processors.
IEEE PACT 1998: 136-141 |
| 5 | EE | Emre Özer,
Sanjeev Banerjia,
Thomas M. Conte:
Unified Assign and Schedule: A New Approach to Scheduling for Clustered Register File Microarchitectures.
MICRO 1998: 308-315 |
| 4 | | Sanjeev Banerjia,
Sumedh W. Sathaye,
Kishore N. Menezes,
Thomas M. Conte:
MPS: Miss-Path Scheduling for Multiple-Issue Processors.
IEEE Trans. Computers 47(12): 1382-1397 (1998) |
| 1997 |
|---|
| 3 | | Sanjeev Banerjia,
William A. Havanki,
Thomas M. Conte:
Treegion Scheduling for Highly Parallel Processors.
Euro-Par 1997: 1074-1078 |
| 1996 |
|---|
| 2 | EE | Thomas M. Conte,
Sanjeev Banerjia,
Sergei Y. Larin,
Kishore N. Menezes,
Sumedh W. Sathaye:
Instruction Fetch Mechanisms for VLIW Architectures with Compressed Encodings.
MICRO 1996: 201-211 |
| 1 | EE | Thomas M. Conte,
Sumedh W. Sathaye,
Sanjeev Banerjia:
A Persistent Rescheduled-page Cache for Low Overhead Object Code Compatibility in VLIW Architectures.
MICRO 1996: 4-13 |
