28. HICSS 1995:
Maui,
Hawaii,
USA - Volume 1
28th Annual Hawaii International Conference on System Sciences (HICSS-28),
January 3-6,
1995,
Kihei,
Maui,
Hawaii,
USA. IEEE Computer Society,
1995,
Volume 1
High Performance Computing and I/O Systems
Reflective Memory and Distributed Shared Memory Architectures for OLTP
- Jelica Protic, Milo Tomasevic, Veljko M. Milutinovic:
A survey of distributed shared memory systems.
74-84
Electronic Edition (link) BibTeX
- Stephen Lucci, Izidor Gertner, Anil Gupta, Uday Hegde:
Reflective-memory multiprocessor.
85-94
Electronic Edition (link) BibTeX
- Mark Natale, Mark Baker, Roger Collins, David Wilson, Stephen Lucci, Izidor Gertner:
Pentium MPP for OLTP applications.
95-102
Electronic Edition (link) BibTeX
- Nicos Vekiarides:
Fault-tolerant disk storage and file systems using reflective memory.
103-113
Electronic Edition (link) BibTeX
- Mark Russinovich, Zary Segall:
Application-transparent checkpointing in Mach 3.O/UX.
114-123
Electronic Edition (link) BibTeX
- Greg Schaffer:
MPP UNIX enhancements for OLTP applications.
124-133
Electronic Edition (link) BibTeX
- Mark Aldred, Ilya Gertner, Stephen McKellar:
A distributed lock manager on fault tolerant MPP .
134-136
Electronic Edition (link) BibTeX
- Gilberto Arnaiz:
Tuning Oracle7 for nCUBE.
137-139
Electronic Edition (link) BibTeX
- Milan Jovanovic, Milo Tomasevic, Veljko M. Milutinovic:
A simulation-based comparison of two reflective memory approaches.
140-
Electronic Edition (link) BibTeX
Instruction Level Parallelism
- Instruction Level Parallelism.
151-152
Electronic Edition (link) BibTeX
- Siamak Arya, Howard Sachs, Sreeram Duvvuru:
An architecture for high instruction level parallelism.
153-162
Electronic Edition (link) BibTeX
- John G. Cleary, Murray Pearson, Husam Kinawi:
The architecture of an optimistic CPU: the WarpEngine.
163-172
Electronic Edition (link) BibTeX
- Sreeram Duvvuru, Siamak Arya:
Evaluation of a branch target address cache.
173-180
Electronic Edition (link) BibTeX
- Thomas Scholz, Michael Schäfers:
An improved dynamic register array concept for high-performance RISC processors.
181-190
Electronic Edition (link) BibTeX
- Marc Tremblay, Bill Joy, Ken Shin:
A three dimensional register file for superscalar processors.
191-201
Electronic Edition (link) BibTeX
- Chi-Hung Chi, Chi-Sum Ho, Siu-Chung Lau:
Reducing memory latency using a small software driven array cache.
202-210
Electronic Edition (link) BibTeX
- Roger A. Bringmann, Scott A. Mahlke, Wen-mei W. Hwu:
A study of the effects of compiler-controlled speculation on instruction and data caches.
211-220
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- J. Stan Cox, David P. Howell, Thomas M. Conte:
Commercializing profile-driven optimization.
221-228
Electronic Edition (link) BibTeX
- Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee D. Coraor:
A comparative evaluation of software techniques to hide memory latency.
229
Electronic Edition (link) BibTeX
Scalable Shared-Memory Architectures
Low Energy ILP Processors
Copyright © Sat May 16 23:14:29 2009
by Michael Ley (ley@uni-trier.de)
