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| 2008 | ||
|---|---|---|
| 2 | EE | Kyuho Shim, Youngrae Cho, Namdo Kim, Hyuncheol Baik, Kyungkuk Kim, Dusung Kim, Jaebum Kim, Byeongun Min, Kyumyung Choi, Maciej J. Ciesielski, Seiyang Yang: A fast two-pass HDL simulation with on-demand dump. ASP-DAC 2008: 422-427 |
| 1 | EE | Kyuho Shim, Kesava R. Talupuru, Maciej J. Ciesielski, Seiyang Yang: Simulation Acceleration with HW Re-Compilation Avoidance. VLSI Design 2008: 487-491 |
| 1 | Hyuncheol Baik | [2] |
| 2 | Youngrae Cho | [2] |
| 3 | Kyumyung Choi | [2] |
| 4 | Maciej J. Ciesielski | [1] [2] |
| 5 | Dusung Kim | [2] |
| 6 | Jaebum Kim | [2] |
| 7 | Kyungkuk Kim | [2] |
| 8 | Namdo Kim | [2] |
| 9 | Byeongun Min | [2] |
| 10 | Kesava R. Talupuru | [1] |
| 11 | Seiyang Yang | [1] [2] |