| |
| 2004 | ||
|---|---|---|
| 2 | EE | Sudheendra Hangal, Durgam Vahia, Chaiyasit Manovit, Juin-Yeu Joseph Lu, Sridhar Narayanan: TSOtool: A Program for Verifying Memory Systems Using the Memory Consistency Model. ISCA 2004: 114-123 |
| 1999 | ||
| 1 | EE | Durgam Vahia, Maciej J. Ciesielski: Transistor level placement for full custom datapath cell design. ISPD 1999: 158-163 |
| 1 | Maciej J. Ciesielski | [1] |
| 2 | Sudheendra Hangal | [2] |
| 3 | Juin-Yeu Joseph Lu | [2] |
| 4 | Chaiyasit Manovit | [2] |
| 5 | Sridhar Narayanan | [2] |