Donald A. Joy

List of publications from the DBLP Bibliography Server - FAQ

1993

2 EE Donald A. Joy, Maciej J. Ciesielski: Clock period minimization with wave pipelining. IEEE Trans. on CAD of Integrated Circuits and Systems 12(4): 461-472 (1993)

1991

1 EE Donald A. Joy, Maciej J. Ciesielski: Placement for Clock Period Minimization With Multiple Wave Propagation. DAC 1991: 640-643

1993
2	EE	Donald A. Joy, Maciej J. Ciesielski: Clock period minimization with wave pipelining. IEEE Trans. on CAD of Integrated Circuits and Systems 12(4): 461-472 (1993)
1991
1	EE	Donald A. Joy, Maciej J. Ciesielski: Placement for Clock Period Minimization With Multiple Wave Propagation. DAC 1991: 640-643

Coauthor Index