| 2008 |
|---|
| 6 | EE | Eric S. Chung,
Eriko Nurvitadhi,
James C. Hoe,
Babak Falsafi,
Ken Mai:
A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs.
FPGA 2008: 77-86 |
| 5 | EE | Eric Menendez,
Ken Mai:
A High-Performance, Low-Overhead, Power-Analysis-Resistant, Single-Rail Logic Style.
HOST 2008: 33-36 |
| 2007 |
|---|
| 4 | EE | Eric S. Chung,
Eriko Nurvitadhi,
James C. Hoe,
Babak Falsafi,
Ken Mai:
PROToFLEX: FPGA-accelerated Hybrid Functional Simulator.
IPDPS 2007: 1-6 |
| 3 | EE | Jangwoo Kim,
Nikos Hardavellas,
Ken Mai,
Babak Falsafi,
James C. Hoe:
Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding.
MICRO 2007: 197-209 |
| 2000 |
|---|
| 2 | EE | Ken Mai,
Tim Paaske,
Nuwan Jayasena,
Ron Ho,
William J. Dally,
Mark Horowitz:
Smart Memories: a modular reconfigurable architecture.
ISCA 2000: 161-171 |
| 1999 |
|---|
| 1 | EE | Ron Ho,
Ken Mai,
Hema Kapadia,
Mark Horowitz:
Interconnect scaling implications for CAD.
ICCAD 1999: 425-429 |
