| 2007 |
|---|
| 12 | EE | P. W. Chandana Prasad,
Ali Assi,
Azam Beg:
Binary Decision Diagrams and neural networks.
The Journal of Supercomputing 39(3): 301-320 (2007) |
| 2006 |
|---|
| 11 | EE | P. W. Chandana Prasad,
Bruce Mills,
Ali Assi,
S. M. N. Arosha Senanayake,
V. C. Prasad:
Evaluation time Estimation for Pass Transistor Logic circuits.
DELTA 2006: 422-428 |
| 10 | | Bruce Mills,
P. W. Chandana Prasad,
Ali Assi:
Formal Presentation of Two Initial Variable Ordering Algorithms for Binary Decision Diagrams.
MSV 2006: 256-262 |
| 9 | EE | Mohamed Raseen,
P. W. Chandana Prasad,
Ali Assi:
An efficient estimation of the ROBDD's complexity.
Integration 39(3): 211-228 (2006) |
| 2005 |
|---|
| 8 | EE | Eric Lebel,
Ali Assi,
Mohamad Sawan:
Field programmable Gm-C array for wide frequency range bandpass filter applications.
ISCAS (3) 2005: 1952-1955 |
| 2004 |
|---|
| 7 | | P. W. Chandana Prasad,
Ali Assi,
Mohamed Raseen:
BDD Minimization Using Graph Parameter Permutation.
ESA/VLSI 2004: 491-496 |
| 6 | | Mohamed Raseen,
Ali Assi,
P. W. Chandana Prasad,
A. Harb:
Effect of Boolean Min-terms on the Complexity of ROBDDs.
International Conference on Computational Intelligence 2004: 454-457 |
| 5 | | P. W. Chandana Prasad,
Ali Assi,
Mohamed Raseen,
A. Harb:
BDD Based Method for Fast Equivalence Checking.
International Conference on Computational Intelligence 2004: 474-477 |
| 4 | EE | Kamal El-Sankary,
Ali Assi,
Mohamad Sawan:
New Sampling Method to Improve the Sfdr of Wide Bandwidth Adc Dedicated to Next Generation Wireless Transceiver.
Journal of Circuits, Systems, and Computers 13(6): 1183-1202 (2004) |
| 2003 |
|---|
| 3 | EE | Kamal El-Sankary,
Ali Assi,
Mohamad Sawan:
New sampling method to improve the SFDR of time-interleaved ADCs.
ISCAS (1) 2003: 833-836 |
| 1997 |
|---|
| 2 | EE | Ali Assi,
Mohamad Sawan,
Rabin Raut:
A New CMOS Tunable Transconductor Dedicated to VHF Continuous-Time Filters.
Great Lakes Symposium on VLSI 1997: 143- |
| 1995 |
|---|
| 1 | EE | Ali Assi,
Bozena Kaminska:
Modeling of communication protocols in VHDL.
Great Lakes Symposium on VLSI 1995: 168-171 |
