| 2008 |
|---|
| 11 | EE | Azam Beg,
P. W. Chandana Prasad,
Walid Ibrahim,
Emad Abu Shama:
Utilizing synthesis to verify Boolean function models.
ISCAS 2008: 1576-1579 |
| 10 | EE | Azam Beg,
P. W. Chandana Prasad,
Ajmal Beg:
Applicability of feed-forward and recurrent neural networks to Boolean function complexity modeling.
Expert Syst. Appl. 34(4): 2436-2443 (2008) |
| 2007 |
|---|
| 9 | EE | P. W. Chandana Prasad,
Ali Assi,
Azam Beg:
Binary Decision Diagrams and neural networks.
The Journal of Supercomputing 39(3): 301-320 (2007) |
| 2006 |
|---|
| 8 | EE | P. W. Chandana Prasad,
Bruce Mills,
Ali Assi,
S. M. N. Arosha Senanayake,
V. C. Prasad:
Evaluation time Estimation for Pass Transistor Logic circuits.
DELTA 2006: 422-428 |
| 7 | | Bruce Mills,
P. W. Chandana Prasad,
Ali Assi:
Formal Presentation of Two Initial Variable Ordering Algorithms for Binary Decision Diagrams.
MSV 2006: 256-262 |
| 6 | EE | Mohamed Raseen,
P. W. Chandana Prasad,
Ali Assi:
An efficient estimation of the ROBDD's complexity.
Integration 39(3): 211-228 (2006) |
| 2004 |
|---|
| 5 | | P. W. Chandana Prasad,
Ali Assi,
Mohamed Raseen:
BDD Minimization Using Graph Parameter Permutation.
ESA/VLSI 2004: 491-496 |
| 4 | | Mohamed Raseen,
Ali Assi,
P. W. Chandana Prasad,
A. Harb:
Effect of Boolean Min-terms on the Complexity of ROBDDs.
International Conference on Computational Intelligence 2004: 454-457 |
| 3 | | P. W. Chandana Prasad,
Ali Assi,
Mohamed Raseen,
A. Harb:
BDD Based Method for Fast Equivalence Checking.
International Conference on Computational Intelligence 2004: 474-477 |
| 2003 |
|---|
| 2 | EE | P. W. Chandana Prasad,
M. Maria Dominic,
Ashutosh Kumar Singh:
Improved Variable Ordering for ROBDDs.
ICADL 2003: 544-547 |
| 1 | EE | P. W. Chandana Prasad,
M. Maria Dominic,
Ashutosh Kumar Singh:
Variable Order Verification Use of Logic Representation.
ICADL 2003: 689 |
