| |
| 2006 | ||
|---|---|---|
| 2 | EE | S. C. Smith: Speedup of NULL convention digital circuits using NULL cycle reduction. Journal of Systems Architecture 52(7): 411-422 (2006) |
| 2005 | ||
| 1 | EE | S. C. Smith: Development of a large word-width high-speed asynchronous multiply and accumulate unit. Integration 39(1): 12-28 (2005) |