| |
| 1997 | ||
|---|---|---|
| 2 | EE | Jonathan Babb, Russell Tessier, Matthew Dahl, Silvina Hanono, David M. Hoki, Anant Agarwal: Logic emulation with virtual wires. IEEE Trans. on CAD of Integrated Circuits and Systems 16(6): 609-626 (1997) |
| 1995 | ||
| 1 | EE | Charles Selvidge, Anant Agarwal, Matthew Dahl, Jonathan Babb: TIERS: Topology Independent Pipelined Routing and Scheduling for VirtualWire Compilation. FPGA 1995: 25-31 |
| 1 | Anant Agarwal | [1] [2] |
| 2 | Jonathan Babb | [1] [2] |
| 3 | Silvina Hanono | [2] |
| 4 | David M. Hoki | [2] |
| 5 | Charles Selvidge | [1] |
| 6 | Russell Tessier | [2] |