| |
| 2008 | ||
|---|---|---|
| 3 | EE | Hao Li, Yue Zhuo: Criticality history guided FPGA placement algorithm for timing optimization. ACM Great Lakes Symposium on VLSI 2008: 267-272 |
| 2007 | ||
| 2 | EE | Yue Zhuo, Hao Li, Qiang Zhou, Yici Cai, Xianlong Hong: New timing and routability driven placement algorithms for FPGA synthesis. ACM Great Lakes Symposium on VLSI 2007: 570-575 |
| 2006 | ||
| 1 | EE | Yue Zhuo, Hao Li, Saraju P. Mohanty: A Congestion Driven Placement Algorithm for FPGA Synthesis. FPL 2006: 1-4 |
| 1 | Yici Cai | [2] |
| 2 | Xianlong Hong | [2] |
| 3 | Hao Li | [1] [2] [3] |
| 4 | Saraju P. Mohanty | [1] |
| 5 | Qiang Zhou | [2] |