2006 |
9 | EE | Ramadass Nagarajan,
Xia Chen,
Robert G. McDonald,
Doug Burger,
Stephen W. Keckler:
Critical path analysis of the TRIPS architecture.
ISPASS 2006: 37-47 |
8 | EE | Karthikeyan Sankaralingam,
Ramadass Nagarajan,
Robert G. McDonald,
Rajagopalan Desikan,
Saurabh Drolia,
M. S. Govindan,
Paul Gratz,
Divya Gulati,
Heather Hanson,
Changkyu Kim,
Haiming Liu,
Nitya Ranganathan,
Simha Sethumadhavan,
Sadia Sharif,
Premkishore Shivakumar,
Stephen W. Keckler,
Doug Burger:
Distributed Microarchitectural Protocols in the TRIPS Prototype Processor.
MICRO 2006: 480-491 |
7 | EE | Aaron Smith,
Ramadass Nagarajan,
Karthikeyan Sankaralingam,
Robert G. McDonald,
Doug Burger,
Stephen W. Keckler,
Kathryn S. McKinley:
Dataflow Predication.
MICRO 2006: 89-102 |
2004 |
6 | EE | Ramadass Nagarajan,
Sundeep K. Kushwaha,
Doug Burger,
Kathryn S. McKinley,
Calvin Lin,
Stephen W. Keckler:
Static Placement, Dynamic Issue (SPDI) Scheduling for EDGE Architectures.
IEEE PACT 2004: 74-84 |
5 | EE | Karthikeyan Sankaralingam,
Ramadass Nagarajan,
Haiming Liu,
Changkyu Kim,
Jaehyuk Huh,
Nitya Ranganathan,
Doug Burger,
Stephen W. Keckler,
Robert G. McDonald,
Charles R. Moore:
TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP.
TACO 1(1): 62-93 (2004) |
2003 |
4 | EE | Karthikeyan Sankaralingam,
Ramadass Nagarajan,
Haiming Liu,
Changkyu Kim,
Jaehyuk Huh,
Doug Burger,
Stephen W. Keckler,
Charles R. Moore:
Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture.
ISCA 2003: 422-433 |
3 | EE | Karthikeyan Sankaralingam,
Ramadass Nagarajan,
Haiming Liu,
Changkyu Kim,
Jaehyuk Huh,
Doug Burger,
Stephen W. Keckler,
Charles R. Moore:
Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture.
IEEE Micro 23(6): 46-51 (2003) |
2002 |
2 | | Prem Melville,
Raymond J. Mooney,
Ramadass Nagarajan:
Content-Boosted Collaborative Filtering for Improved Recommendations.
AAAI/IAAI 2002: 187-192 |
2001 |
1 | EE | Ramadass Nagarajan,
Karthikeyan Sankaralingam,
Doug Burger,
Stephen W. Keckler:
A design space evaluation of grid processor architectures.
MICRO 2001: 40-51 |