| 2008 |
|---|
| 10 | EE | Ashok V. Krishnamoorthy,
Jon Lexau,
Xuezhe Zheng,
John E. Cunningham,
Ron Ho,
Ola Tørudbakken:
Optical Interconnects for Present and Future High-Performance Computing Systems.
Hot Interconnects 2008: 175-177 |
| 2007 |
|---|
| 9 | EE | Frankie Liu,
Ron Ho,
Robert J. Drost,
Scott Fairbanks:
On-chip samplers for test and debug of asynchronous circuits.
ASYNC 2007: 153-162 |
| 8 | EE | Dinesh Patil,
Omid Azizi,
Mark Horowitz,
Ron Ho,
Rajesh Ananthraman:
Robust Energy-Efficient Adder Topologies.
IEEE Symposium on Computer Arithmetic 2007: 16-28 |
| 7 | EE | John D. Owens,
William J. Dally,
Ron Ho,
D. N. Jayasimha,
Stephen W. Keckler,
Li-Shiuan Peh:
Research Challenges for On-Chip Interconnection Networks.
IEEE Micro 27(5): 96-108 (2007) |
| 2005 |
|---|
| 6 | EE | Robert J. Drost,
Craig Forrest,
Bruce Guenin,
Ron Ho,
Ashok V. Krishnamoorthy,
Danny Cohen,
John E. Cunningham,
Bernard Tourancheau,
Arthur Zingher,
Alex Chow,
Gary Lauterbach,
Ivan E. Sutherland:
Challenges in Building a Flat-Bandwidth Memory Hierarchy for a Large-Scale Computer with Proximity Communication.
Hot Interconnects 2005: 13-22 |
| 5 | EE | Ron Ho:
High-performance ULSI: the real limiter to interconnect scaling.
SLIP 2005: 3 |
| 2004 |
|---|
| 4 | EE | Ron Ho,
Jonathan Gainsley,
Robert J. Drost:
Long Wires and Asynchronous Control.
ASYNC 2004: 240-249 |
| 3 | | Yun Zhang,
Mihai Burcea,
Victor Cheng,
Ron Ho,
Michael Voss:
An Adaptive OpenMP Loop Scheduler for Hyperthreaded SMPs.
ISCA PDCS 2004: 256-263 |
| 2000 |
|---|
| 2 | EE | Ken Mai,
Tim Paaske,
Nuwan Jayasena,
Ron Ho,
William J. Dally,
Mark Horowitz:
Smart Memories: a modular reconfigurable architecture.
ISCA 2000: 161-171 |
| 1999 |
|---|
| 1 | EE | Ron Ho,
Ken Mai,
Hema Kapadia,
Mark Horowitz:
Interconnect scaling implications for CAD.
ICCAD 1999: 425-429 |
