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| 2008 | ||
|---|---|---|
| 2 | EE | Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer: A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs. FPGA 2008: 87-96 |
| 1 | EE | Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer: Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs. ISPASS 2008: 1-10 |
| 1 | Arvind | [1] [2] |
| 2 | Joel S. Emer | [1] [2] |
| 3 | Michael Pellauer | [1] [2] |
| 4 | Muralidaran Vijayaraghavan | [1] [2] |