| 2007 |
|---|
| 17 | EE | Chih-Chi Cheng,
Chao-Tsung Huang,
Ching-Yeh Chen,
Chung-Jr Lian,
Liang-Gee Chen:
On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform.
IEEE Trans. Circuits Syst. Video Techn. 17(7): 814-822 (2007) |
| 2006 |
|---|
| 16 | EE | Ching-Yeh Chen,
Chao-Tsung Huang,
Yi-Hau Chen,
Liang-Gee Chen:
Level C+ data reuse scheme for motion estimation with corresponding coding orders.
IEEE Trans. Circuits Syst. Video Techn. 16(4): 553-558 (2006) |
| 2005 |
|---|
| 15 | EE | Ching-Yeh Chen,
Chao-Tsung Huang,
Yi-Hua Chen,
Chung-Jr Lian,
Liang-Gee Chen:
System analysis of VLSI architecture for motion-compensated temporal filtering.
ICIP (3) 2005: 992-995 |
| 14 | EE | Tung-Chien Chen,
Yu-Wen Huang,
Chuan-Yung Tsai,
Chao-Tsung Huang,
Liang-Gee Chen:
Single reference frame multiple current macroblocks scheme for multi-frame motion estimation in H.264/AVC.
ISCAS (2) 2005: 1790-1793 |
| 13 | EE | Chih-Chi Cheng,
Chao-Tsung Huang,
Po-Chih Tseng,
Chia-Ho Pan,
Liang-Gee Chen:
Multiple-lifting scheme: memory-efficient VLSI implementation for line-based 2-D DWT.
ISCAS (5) 2005: 5190-5193 |
| 12 | EE | Chao-Tsung Huang,
Po-Chih Tseng,
Liang-Gee Chen:
Generic RAM-based architectures for two-dimensional discrete wavelet transform with line-based method.
IEEE Trans. Circuits Syst. Video Techn. 15(7): 910-920 (2005) |
| 11 | EE | Chao-Tsung Huang,
Po-Chih Tseng,
Liang-Gee Chen:
Analysis and VLSI architecture for 1-D and 2-D discrete wavelet transform.
IEEE Transactions on Signal Processing 53(4): 1575-1586 (2005) |
| 10 | EE | Chao-Tsung Huang,
Po-Chih Tseng,
Liang-Gee Chen:
VLSI Architecture for Lifting-Based Shape-Adaptive Discrete Wavelet Transform with Odd-Symmetric Filters.
VLSI Signal Processing 40(2): 175-188 (2005) |
| 9 | EE | Chao-Tsung Huang,
Po-Chih Tseng,
Liang-Gee Chen:
VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization.
VLSI Signal Processing 40(3): 343-353 (2005) |
| 8 | EE | Po-Chih Tseng,
Chao-Tsung Huang,
Liang-Gee Chen:
Reconfigurable Discrete Wavelet Transform Processor for Heterogeneous Reconfigurable Multimedia Systems.
VLSI Signal Processing 41(1): 35-47 (2005) |
| 2004 |
|---|
| 7 | | Po-Chih Tseng,
Chao-Tsung Huang,
Liang-Gee Chen:
Reconfigurable discrete cosine transform processor for object-based video signal processing.
ISCAS (2) 2004: 353-356 |
| 6 | | Chao-Tsung Huang,
Po-Chih Tseng,
Liang-Gee Chen:
B-spline factorization-based architecture for inverse discrete wavelet transform.
ISCAS (2) 2004: 829-832 |
| 2003 |
|---|
| 5 | | Chao-Tsung Huang,
Po-Chih Tseng,
Liang-Gee Chen:
Hardware implementation of shape-adaptive discrete wavelet transform with the JPEG2000 defaulted (9, 7) filter bank.
ICIP (2) 2003: 571-574 |
| 2002 |
|---|
| 4 | EE | Po-Chih Tseng,
Chao-Tsung Huang,
Liang-Gee Chen:
Generic RAM-based architecture for two-dimensional discrete wavelet transform with line-based method.
APCCAS (1) 2002: 363-366 |
| 3 | EE | Chao-Tsung Huang,
Po-Chih Tseng,
Liang-Gee Chen:
Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform.
APCCAS (1) 2002: 383-388 |
| 2 | EE | Chao-Tsung Huang,
Po-Chih Tseng,
Liang-Gee Chen:
Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design method.
ISCAS (5) 2002: 565-568 |
| 1 | | Po-Chih Tseng,
Chao-Tsung Huang,
Liang-Gee Chen:
VLSI implementation of shape-adaptive discrete wavelet transform.
VCIP 2002: 655-666 |
