| 2008 |
|---|
| 5 | EE | Yi-Hau Chen,
Tzu-Der Chuang,
Yu-Han Chen,
Chen-Han Tsai,
Liang-Gee Chen:
Frame-parallel design strategy for high definition B-frame H.264/AVC encoder.
ISCAS 2008: 29-32 |
| 2006 |
|---|
| 4 | EE | Chi-Sun Tang,
Chen-Han Tsai,
Shao-Yi Chien,
Liang-Gee Chen:
Algorithm and hardware architecture design for weighted prediction in H.264/MPEG-4 AVC.
ISCAS 2006 |
| 3 | EE | Yu-Jen Chen,
Chen-Han Tsai,
Liang-Gee Chen:
Architecture design of area-efficient SRAM-based multi-symbol arithmetic encoder in H.264/AVC.
ISCAS 2006 |
| 2 | EE | Tung-Chien Chen,
Shao-Yi Chien,
Yu-Wen Huang,
Chen-Han Tsai,
Ching-Yeh Chen,
To-Wei Chen,
Liang-Gee Chen:
Analysis and architecture design of an HDTV720p 30 frames/s H.264/AVC encoder.
IEEE Trans. Circuits Syst. Video Techn. 16(6): 673-688 (2006) |
| 1 | EE | Yu-Wen Huang,
Ching-Yeh Chen,
Chen-Han Tsai,
Chun-Fu Shen,
Liang-Gee Chen:
Survey on Block Matching Motion Estimation Algorithms and Architectures with New Results.
VLSI Signal Processing 42(3): 297-320 (2006) |
