| 2008 |
|---|
| 9 | EE | Chih-Chi Cheng,
Chia-Hua Lin,
Chung-Te Li,
Samuel C. Chang,
Liang-Gee Chen:
iVisual: an intelligent visual sensor SoC with 2790fps CMOS image sensor and 205GOPS/W vision processor.
DAC 2008: 90-95 |
| 8 | EE | Myong Hyon Cho,
Chih-Chi Cheng,
Michel Kinsy,
G. Edward Suh,
Srinivas Devadas:
Diastolic arrays: throughput-driven reconfigurable computing.
ICCAD 2008: 457-464 |
| 7 | EE | Yi-Hau Chen,
Chih-Chi Cheng,
Tzu-Der Chuang,
Ching-Yeh Chen,
Shao-Yi Chien,
Liang-Gee Chen:
Efficient Architecture Design of Motion-Compensated Temporal Filtering/Motion Compensated Prediction Engine.
IEEE Trans. Circuits Syst. Video Techn. 18(1): 98-109 (2008) |
| 2007 |
|---|
| 6 | EE | Chih-Chi Cheng,
Chao-Tsung Huang,
Ching-Yeh Chen,
Chung-Jr Lian,
Liang-Gee Chen:
On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform.
IEEE Trans. Circuits Syst. Video Techn. 17(7): 814-822 (2007) |
| 2006 |
|---|
| 5 | EE | Yi-Hau Chen,
Ching-Yeh Chen,
Chih-Chi Cheng,
Liang-Gee Chen:
Scalable Rate-Distortion-Computation Hardware Accelerator for MCTF and ME.
ICME 2006: 365-368 |
| 4 | EE | Chih-Chi Cheng,
Ching-Yeh Chen,
Yi-Hau Chen,
Liang-Gee Chen:
Analysis and VLSI architecture of update step in motion-compensated temporal filtering.
ISCAS 2006 |
| 3 | EE | Ching-Yeh Chen,
Yi-Hau Chen,
Chih-Chi Cheng,
Liang-Gee Chen:
Frame-level data reuse for motion-compensated temporal filtering.
ISCAS 2006 |
| 2005 |
|---|
| 2 | EE | Chih-Chi Cheng,
Chao-Tsung Huang,
Po-Chih Tseng,
Chia-Ho Pan,
Liang-Gee Chen:
Multiple-lifting scheme: memory-efficient VLSI implementation for line-based 2-D DWT.
ISCAS (5) 2005: 5190-5193 |
| 1 | EE | Chia-Ho Pan,
I-Hsien Lee,
Sheng-Chieh Huang,
Chih-Chi Cheng,
Chung-Jr Lian,
Liang-Gee Chen:
Application Layer Error Correction Scheme for Video Header Protection on Wireless Network.
ISM 2005: 499-505 |
