2005 |
10 | EE | Hung-Chi Fang,
Yu-Wei Chang,
Tu-Chih Wang,
Chung-Jr Lian,
Liang-Gee Chen:
Parallel embedded block coding architecture for JPEG 2000.
IEEE Trans. Circuits Syst. Video Techn. 15(9): 1086-1097 (2005) |
2003 |
9 | EE | Hung-Chi Fang,
Tu-Chih Wang,
Chung-Jr Lian,
Te-Hao Chang,
Liang-Gee Chen:
High speed memory efficient EBCOT architecture for JPEG2000.
ISCAS (2) 2003: 736-739 |
8 | EE | Yu-Wen Huang,
Tu-Chih Wang,
Bing-Yu Hsieh,
Liang-Gee Chen:
Hardware architecture design for variable block size motion estimation in MPEG-4 AVC/JVT/ITU-T H.264.
ISCAS (2) 2003: 796-799 |
7 | EE | Tu-Chih Wang,
Yu-Wen Huang,
Hung-Chi Fang,
Liang-Gee Chen:
Parallel 4/spl times/4 2D transform and inverse transform architecture for MPEG-4 AVC/H.264.
ISCAS (2) 2003: 800-803 |
6 | | Bing-Yu Hsieh,
Yu-Wen Huang,
Tu-Chih Wang,
Shao-Yi Chien,
Liang-Gee Chen:
Fast motion estimation algorithm for H.264/MPEG-4 AVC by using multiple reference frame skipping criteria.
VCIP 2003: 1551-1560 |
2002 |
5 | EE | Hung-Chi Fang,
Tu-Chih Wang,
Liang-Gee Chen:
Real-time deblocking filter for MPEG-4 systems.
APCCAS (1) 2002: 541-544 |
4 | | Tu-Chih Wang,
Hung-Chi Fang,
Liang-Gee Chen:
Low-delay and error-robust wireless video transmission for video communications.
IEEE Trans. Circuits Syst. Video Techn. 12(12): 1049- (2002) |
2001 |
3 | | Jun-Fu Shen,
Tu-Chih Wang,
Liang-Gee Chen:
A novel low-power full-search block-matching motion-estimation design for H.263+.
IEEE Trans. Circuits Syst. Video Techn. 11(7): 890-897 (2001) |
2 | EE | Chien-Yu Chen,
Zhong-Lan Yang,
Tu-Chih Wang,
Liang-Gee Chen:
A Programmable Parallel VLSI Architecture for 2-D Discrete Wavelet Transform.
VLSI Signal Processing 28(3): 151-163 (2001) |
1999 |
1 | EE | Jun-Fu Shen,
Liang-Gee Chen,
Hao-Chieh Chang,
Tu-Chih Wang:
Low power full-search block-matching motion estimation chip for H.263+.
ISCAS (4) 1999: 299-302 |