Akio Hirata
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1998
1
EE
Akio Hirata,
Hidetoshi Onodera
,
Keikichi Tamaru
: Proposal of a timing model for CMOS logic gates driving a CRC load.
ICCAD 1998
: 537-544
Coauthor
Index
1
Hidetoshi Onodera
[
1
]
2
Keikichi Tamaru
[
1
]
Copyright ©
Sun May 17 03:24:02 2009 by
Michael Ley
(
ley@uni-trier.de
)
