| |
| 2008 | ||
|---|---|---|
| 2 | EE | Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera: Statistical gate delay model for Multiple Input Switching. ASP-DAC 2008: 286-291 |
| 2007 | ||
| 1 | EE | Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera: Worst-case delay analysis considering the variability of transistors and interconnects. ISPD 2007: 35-42 |
| 1 | Hidetoshi Onodera | [1] [2] |
| 2 | Akira Tsuchiya | [1] [2] |