| 2005 |
|---|
| 6 | EE | Terence B. Hook,
Ronald J. Bolam,
William Clark,
Jay S. Burnham,
Nivo Rovedo,
Laura Schutz:
Negative bias temperature instability on three oxide thicknesses (1.4/2.2/5.2 nm) with nitridation variations and deuteration.
Microelectronics Reliability 45(1): 47-56 (2005) |
| 2003 |
|---|
| 5 | EE | Randy W. Mann,
W. W. (Bill) Abadeer,
Matthew J. Breitwisch,
O. Bula,
Jeff S. Brown,
Bryant C. Colwill,
Peter E. Cottrell,
William T. Crocco Jr.,
Stephen S. Furkay,
Michael J. Hauser,
Terence B. Hook,
Dennis Hoyniak,
James M. Johnson,
Chung Hon Lam,
Rebecca D. Mih,
J. Rivard,
Atsushi Moriwaki,
E. Phipps,
Christopher S. Putnam,
BethAnn Rainey,
James J. Toomey,
Mohammad Imran Younus:
Ultralow-power SRAM technology.
IBM Journal of Research and Development 47(5-6): 553-566 (2003) |
| 2001 |
|---|
| 4 | EE | Stephen V. Kosonocky,
Michael Immediato,
Peter E. Cottrell,
Terence B. Hook,
Randy W. Mann,
Jeff Brown:
Enchanced multi-threshold (MTCMOS) circuits using variable well bias.
ISLPED 2001: 165-169 |
| 3 | EE | Terence B. Hook,
David Harmon,
Chuan Lin:
Plasma process-induced damage on thick (6.8 nm) and thin (3.5 nm) gate oxide: parametric shifts, hot-carrier response, and dielectric integrity degradation.
Microelectronics Reliability 41(5): 751-765 (2001) |
| 1999 |
|---|
| 2 | EE | Terence B. Hook,
Jay S. Burnham,
Ronald J. Bolam:
Nitrided gate oxides for 3.3-V logic application: Reliability and device design considerations.
IBM Journal of Research and Development 43(3): 393-406 (1999) |
| 1992 |
|---|
| 1 | EE | Terence B. Hook:
Automatic extraction of circuit models from layout artwork for a BiCMOS technology.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(6): 732-738 (1992) |
