| 2008 |
|---|
| 4 | EE | Philipp V. Panitz,
Markus Olbrich,
Erich Barke,
Markus Bühler,
Jürgen Koehl:
Considering possible opens in non-tree topology wire delay calculation.
ACM Great Lakes Symposium on VLSI 2008: 17-22 |
| 2006 |
|---|
| 3 | EE | Markus Bühler,
Jürgen Koehl,
Jeanne Bickford,
Jason Hibbeler,
Ulf Schlichtmann,
R. Sommer,
Michael Pronath,
Andreas Ripp:
DFM/DFY design for manufacturability and yield - influence of process variations in digital, analog and mixed-signal circuit design.
DATE 2006: 387-392 |
| 2 | EE | Jeanne Bickford,
Jason Hibbeler,
Markus Bühler,
Jürgen Koehl,
Dirk Muller,
Sven Peyer,
Christian Schulte:
Yield Improvement by Local Wiring Redundancy.
ISQED 2006: 473-478 |
| 1999 |
|---|
| 1 | EE | Markus Bühler,
Matthias Papesch,
K. Kapp,
Utz G. Baitinger:
Efficient Switching Activity Simulation under a Real Delay Model Using a Bitparallel Approach.
DATE 1999: 459- |
