Scott C. Smith

2007
15	EE	Scott C. Smith: Design of a logic element for implementing an asynchronous FPGA. FPGA 2007: 13-22
14	EE	Venkat Satagopan, Bonita Bhaskaran, Waleed Al-Assadi, Scott C. Smith, Sindhu Kakarla: DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits. IEEE Trans. VLSI Syst. 15(10): 1155-1159 (2007)
13	EE	Scott C. Smith: Design of an FPGA Logic Element for Implementing Asynchronous NULL Convention Logic Circuits. IEEE Trans. VLSI Syst. 15(6): 672-683 (2007)
12	EE	Venkat Satagopan, Bonita Bhaskaran, Anshul Singh, Scott C. Smith: Automated energy calculation and estimation for delay-insensitive digital circuits. Microelectronics Journal 38(10-11): 1095-1107 (2007)
2005
11		Anshul Singh, Scott C. Smith: Using a VHDL Testbench for Transistor-Level Simulation and Energy Calculation. CDES 2005: 115-121
10		Bonita Bhaskaran, Venkat Satagopan, Scott C. Smith: High-Speed Energy Estimation for Delay-Insensitive Circuits. CDES 2005: 35-41
9		Bonita Bhaskaran, Venkat Satagopan, Waleed Al-Assadi, Scott C. Smith: Implementation of Design For Test for Asynchronous NCL Designs. CDES 2005: 78-84
2004
8		Scott C. Smith: Designing NULL Convention Combinational Circuits to Fully Utilize Gate-Level Pipelining for Maximum Throughput. ESA/VLSI 2004: 407-412
7		Scott C. Smith: Design of a NULL Convention Self-Timed Divider. ESA/VLSI 2004: 447-453
6	EE	Scott C. Smith, Ronald F. DeMara, Jiann S. Yuan, D. Ferguson, D. Lamb: Optimization of NULL convention self-timed circuits. Integration 37(3): 135-165 (2004)
2003
5		Scott C. Smith: Completion-Completeness for NULL Convention Digital Circuits Utilizing the Bit-Wise Completion Strategy. VLSI 2003: 143-149
4		Satish K. Bandapati, Scott C. Smith: Design and Characterization of NULL Convention Arithmetic Logic Units. VLSI 2003: 178-184
3	EE	Satish K. Bandapati, Scott C. Smith, Minsu Choi: Design and Characterization of Null Convention Self-Timed Multipliers. IEEE Design & Test of Computers 20(6): 26-36 (2003)
2002
2	EE	Scott C. Smith: Speedup of Self-Timed Digital Systems Using Early Completion. ISVLSI 2002: 107-116
2001
1	EE	Scott C. Smith, Ronald F. DeMara, Jiann S. Yuan, M. Hagedorn, D. Ferguson: Delay-insensitive gate-level pipelining. Integration 30(2): 103-131 (2001)

Coauthor Index

1	Waleed Al-Assadi	[9] [14]
2	Satish K. Bandapati	[3] [4]
3	Bonita Bhaskaran	[9] [10] [12] [14]
4	Minsu Choi	[3]
5	Ronald F. DeMara	[1] [6]
6	D. Ferguson	[1] [6]
7	M. Hagedorn	[1]
8	Sindhu Kakarla	[14]
9	D. Lamb	[6]
10	Venkat Satagopan	[9] [10] [12] [14]
11	Anshul Singh	[11] [12]
12	Jiann S. Yuan	[1] [6]

Colors in the list of coauthors