| 2007 |
|---|
| 8 | | Antonio Petraglia,
Volnei A. Pedroni,
Gert Cauwenberghs:
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2007, Copacabana, Rio de Janeiro, Brazil, September 3-6, 2007
ACM 2007 |
| 2006 |
|---|
| 7 | EE | Volnei A. Pedroni,
R. U. Pedroni:
PLL-less clock multiplier with self-adjusting phase symmetry.
ISCAS 2006 |
| 6 | EE | Volnei A. Pedroni:
Phase sampling: a new approach to the design of LF direct digital frequency synthesizers.
ISCAS 2006 |
| 2004 |
|---|
| 5 | EE | Fabio Sousa,
Volker Mauer,
Neimar Duarte,
Ricardo P. Jasinski,
Volnei A. Pedroni:
Taking advantage of LVDS input buffers to implement sigma-delta A/D converters in FPGAs.
ISCAS (1) 2004: 1088-1091 |
| 4 | | Volnei A. Pedroni:
Compact Hamming-Comparator-based rank order filter for digital VLSI and FPGA implementations.
ISCAS (2) 2004: 585-588 |
| 2003 |
|---|
| 3 | EE | Volnei A. Pedroni:
Teaching Design-Oriented VHDL.
MSE 2003: 6-7 |
| 2 | | Volnei A. Pedroni:
High-Resolution WTA-MAX Circuit for Large Networks.
VLSI 2003: 150-154 |
| 1994 |
|---|
| 1 | EE | Gert Cauwenberghs,
Volnei A. Pedroni:
A Charge-Based Parallel Analog Vector Quantizer.
NIPS 1994: 779-787 |
