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J. Biesenack

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1994
4EENorbert Wehn, J. Biesenack, Peter Duzy, T. Langmaier, Michael Münch, Michael Pilsl, S. Rumler: Scheduling of behavioral VHDL by retiming techniques. EURO-DAC 1994: 546-551
1993
3EEJ. Biesenack, M. Koster, A. Langmaier, S. Ledeux, S. Marz, Michael Payer, Michael Pilsl, S. Rumler, H. Soukup, Norbert Wehn, Peter Duzy: The Siemens high-level synthesis system CALLAS. IEEE Trans. VLSI Syst. 1(3): 244-253 (1993)
1992
2 J. Biesenack, Norbert Wehn, A. Stoll, Michael Payer: Data Part Optimizations in the CALLAS Synthesis Environment. Synthesis for Control Dominated Circuits 1992: 263-274
1991
1 Norbert Wehn, J. Biesenack, Michael Pilsl: A New Approach to Multiplexer Minimisation in the CALLAS Synthesis Environment. VLSI 1991: 203-213

Coauthor Index

1Peter Duzy [3] [4]
2M. Koster [3]
3A. Langmaier [3]
4T. Langmaier [4]
5S. Ledeux [3]
6S. Marz [3]
7Michael Münch [4]
8Michael Payer [2] [3]
9Michael Pilsl [1] [3] [4]
10S. Rumler [3] [4]
11H. Soukup [3]
12A. Stoll [2]
13Norbert Wehn [1] [2] [3] [4]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)