| 2008 |
|---|
| 7 | EE | Seongjae Cho,
Il Han Park,
Jung Hoon Lee,
Jang-Gn Yun,
Doo-Hyun Kim,
Jong Duk Lee,
Hyungcheol Shin,
Byung-Gook Park:
Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI).
IEICE Transactions 91-C(5): 731-735 (2008) |
| 6 | EE | Jang-Gn Yun,
Il Han Park,
Seongjae Cho,
Jung Hoon Lee,
Doo-Hyun Kim,
Gil Sung Lee,
Yoon Kim,
Jong Duk Lee,
Byung-Gook Park:
Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme.
IEICE Transactions 91-C(5): 742-746 (2008) |
| 2007 |
|---|
| 5 | EE | Jong Pil Kim,
Woo Young Choi,
Jae Young Song,
Seongjae Cho,
Sang Wan Kim,
Jong Duk Lee,
Byung-Gook Park:
Design and Simulation of Asymmetric MOSFETs.
IEICE Transactions 90-C(5): 978-982 (2007) |
| 4 | EE | Seongjae Cho,
Jang-Gn Yun,
Il Han Park,
Jung Hoon Lee,
Jong Pil Kim,
Jong Duk Lee,
Hyungcheol Shin,
Byung-Gook Park:
Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices.
IEICE Transactions 90-C(5): 988-993 (2007) |
| 2004 |
|---|
| 3 | EE | Hyuck In Kwon,
In Man Kang,
Byung-Gook Park,
Jong Duk Lee,
Sang Sik Park,
Jung Chak Ahn,
Yong Hee Lee:
Effects of electrical stress on mid-gap interface trap density and capture cross sections in n-MOSFETs characterized by pulsed interface probing measurements.
Microelectronics Reliability 44(1): 47-51 (2004) |
| 2003 |
|---|
| 2 | EE | Woo Young Choi,
Jong Duk Lee,
Byung-Gook Park:
Reverse-order source/drain formation with double offset spacer (RODOS) for CMOS low-power, high-speed and low-noise amplifiers.
ISLPED 2003: 189-192 |
| 1 | EE | Ki-Whan Song,
Sang-Hoon Lee,
Dae Hwan Kim,
Kyung Rok Kim,
Jaewoo Kyung,
Gwanghyeon Baek,
Chun-An Lee,
Jong Duk Lee,
Byung-Gook Park:
Complementary Self-Biased Scheme for the Robust Design of CMOS/SET Hybrid Multi-Valued Logic.
ISMVL 2003: 267-272 |
