| 2008 |
|---|
| 7 | EE | Yuki Watanabe,
Naofumi Homma,
Katsuhiko Degawa,
Takafumi Aoki,
Tatsuo Higuchi:
High-Level Design of Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language.
ISMVL 2008: 112-117 |
| 2007 |
|---|
| 6 | EE | Naofumi Homma,
Katsuhiko Degawa,
Takafumi Aoki,
Tatsuo Higuchi:
Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams.
ISMVL 2007: 31 |
| 2006 |
|---|
| 5 | EE | Katsuhiko Degawa,
Takafumi Aoki,
Tatsuo Higuchi,
Hiroshi Inokawa,
Katsuhiko Nishiguchi,
Yasuo Takahashi:
A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors.
ISMVL 2006: 19 |
| 2005 |
|---|
| 4 | EE | Katsuhiko Degawa,
Takafumi Aoki,
Hiroshi Inokawa,
Tatsuo Higuchi,
Yasuo Takahashi:
A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors.
ISMVL 2005: 32-38 |
| 2004 |
|---|
| 3 | EE | Katsuhiko Degawa,
Takafumi Aoki,
Tatsuo Higuchi,
Hiroshi Inokawa,
Yasuo Takahashi:
A Single-Electron-Transistor Logic Gate Family and Its Application - Part I: Basic Components for Binary, Multiple-Valued and Mixed-Mode Logic.
ISMVL 2004: 262-268 |
| 2 | EE | Hiroshi Inokawa,
Yasuo Takahashi,
Katsuhiko Degawa,
Takafumi Aoki,
Tatsuo Higuchi:
A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions.
ISMVL 2004: 269-274 |
| 2003 |
|---|
| 1 | EE | Katsuhiko Degawa,
Takafumi Aoki,
Tatsuo Higuchi:
A Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic.
ISMVL 2003: 213-220 |
