Andrew R. Pleszkun

2003
23	EE	Stephen Aiken, Dirk Grunwald, Andrew R. Pleszkun, Jesse Willek: A Performance Analysis of the iSCSI Protocol. IEEE Symposium on Mass Storage Systems 2003: 123-134
1998
22	EE	James E. Smith, Andrew R. Pleszkun: Implementation of Precise Interupts in Pipelined Processors. 25 Years ISCA: Retrospectives and Reprints 1998: 291-299
21	EE	Dirk Grunwald, Artur Klauser, Srilatha Manne, Andrew R. Pleszkun: Confidence Estimation for Speculation Control. ISCA 1998: 122-131
1995
20	EE	Gary S. Tyson, Matthew K. Farrens, John Matthews, Andrew R. Pleszkun: A modified approach to data cache management. MICRO 1995: 93-103
1994
19		Matthew K. Farrens, Gary S. Tyson, Andrew R. Pleszkun: A Study of Single-Chip Processor/Cache Organizations for Large Numbers of Transistors. ISCA 1994: 338-347
18	EE	Andrew R. Pleszkun: Techniques for compressing program address traces. MICRO 1994: 32-39
1992
17	EE	Gary S. Tyson, Matthew K. Farrens, Andrew R. Pleszkun: MISC: a Multiple Instruction Stream Computer. MICRO 1992: 193-196
1991
16	EE	Matthew K. Farrens, Andrew R. Pleszkun: Strategies for Achieving Improved Processor Throughput. ISCA 1991: 362-369
15		Matthew K. Farrens, Andrew R. Pleszkun: Implementation of the PIPE Processor. IEEE Computer 24(1): 65-69 (1991)
1990
14	EE	Matthew K. Farrens, Andrew R. Pleszkun: An evaluation of functional unit lengths for single-chip processors. MICRO 1990: 209-215
1989
13	EE	Matthew K. Farrens, Andrew R. Pleszkun: Improving Performance of Small On-Chip Instruction Caches. ISCA 1989: 234-241
1988
12		Andrew R. Pleszkun, Gurindar S. Sohi: The Performance Potential of Multiple Functional Unit Processors. ISCA 1988: 37-44
11	EE	Andrew R. Pleszkun, Gurindar S. Sohi: Multiple instruction issue and single-chip processors. MICRO 1988: 64-66
10		James E. Smith, Andrew R. Pleszkun: Implementing Precise Interrupts in Pipelined Processors. IEEE Trans. Computers 37(5): 562-573 (1988)
1987
9		Andrew R. Pleszkun, James R. Goodman, Wei-Chung Hsu, R. T. Joersz, George E. Bier, Philip J. Woest, P. B. Schechter: WISQ: A Restartable Architecture Using Queues. ISCA 1987: 290-299
8		Andrew R. Pleszkun, Matthew Thazhuthaveetil: The Architecture of Lisp Machines. IEEE Computer 20(3): 35-44 (1987)
7		Matthew Thazhuthaveetil, Andrew R. Pleszkun: On the Structural Locality of Reference in LISP List Access Streams. Inf. Process. Lett. 26(2): 105-110 (1987)
1986
6		Andrew R. Pleszkun, Gurindar S. Sohi, Bassam Z. Kahhaleh, Edward S. Davidson: Features of the Structured Memory Access (SMA) Architecture. COMPCON 1986: 259-265
5		Andrew R. Pleszkun, Matthew Thazhuthaveetil: An Architecture for Efficient Lisp List Access. ISCA 1986: 191-198
1985
4	EE	George E. Bier, Andrew R. Pleszkun: An algorithm for design rule checking on a multiprocessor. DAC 1985: 299-304
3		James R. Goodman, Jian-tu Hsieh, Koujuch Liou, Andrew R. Pleszkun, P. B. Schechter, Honesty C. Young: PIPE: A VLSI Decoupled Architecture. ISCA 1985: 20-27
2		James E. Smith, Andrew R. Pleszkun: Implementation of Precise Interrupts in Pipelined Processors. ISCA 1985: 36-44
1983
1		Andrew R. Pleszkun, Edward S. Davidson: Structured Memory Access Architecture. ICPP 1983: 461-471

Coauthor Index

1	Stephen Aiken	[23]
2	George E. Bier	[4] [9]
3	Edward S. Davidson	[1] [6]
4	Matthew K. Farrens	[13] [14] [15] [16] [17] [19] [20]
5	James R. Goodman	[3] [9]
6	Dirk Grunwald	[21] [23]
7	Jian-tu Hsieh	[3]
8	Wei-Chung Hsu	[9]
9	R. T. Joersz	[9]
10	Bassam Z. Kahhaleh	[6]
11	Artur Klauser	[21]
12	Koujuch Liou	[3]
13	Srilatha Manne	[21]
14	John Matthews	[20]
15	P. B. Schechter	[3] [9]
16	James E. Smith	[2] [10] [22]
17	Gurindar S. Sohi	[6] [11] [12]
18	Matthew Thazhuthaveetil	[5] [7] [8]
19	Gary S. Tyson	[17] [19] [20]
20	Jesse Willek	[23]
21	Philip J. Woest	[9]
22	Honesty C. Young	[3]

Colors in the list of coauthors