5. HPCA 1999: Orlando, FL, USA

Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, 9-12 January 1999, Orlando, FL, USA. IEEE Computer Society. online publication: http: //www.computer.org/proceedings/hpca/0004/0004toc.htm

Performance Enhancements

Tarun Nakra, Rajiv Gupta, Mary Lou Soffa:
Global Context-Based Value Prediction. 4-12
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David Brooks, Margaret Martonosi:
Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance. 13-22
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Murthy Durbhakula, Vijay S. Pai, Sarita V. Adve:
Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors. 23-32
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Kang Su Gatlin, Larry Carter:
Memory Hierarchy Considerations for Fast Transpose and Bit-Reversals. 33-
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Simultaneous Multithreading

Steven Wallace, Dean M. Tullsen, Brad Calder:
Instruction Recycling on a Multiple-Path Processor. 44-53
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Dean M. Tullsen, Jack L. Lo, Susan J. Eggers, Henry M. Levy:
Supporting Fine-Grained Synchronization on a Simultaneous Multithreading Processor. 54-58
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Joan-Manuel Parcerisa, Antonio González:
The Synergy of Multithreading and Access/Execute Decoupling. 59-63
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Sébastien Hily, André Seznec:
Out-of-Order Execution may not be Cost-Effective on Processors Featuring Simultaneous Multithreading. 64-
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Memory Systems

John B. Carter, Wilson C. Hsieh, Leigh Stoller, Mark R. Swanson, Lixin Zhang, Erik Brunvand, Al Davis, Chen-Chi Kuo, Ravindra Kuramkote, Michael Parker, Lambert Schaelicke, Terry Tateyama:
Impulse: Building a Smarter Memory Controller. 70-79
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Sung I. Hong, Sally A. McKee, Maximo H. Salinas, Robert H. Klenke, James H. Aylor, William A. Wulf:
Access Order and Effective Bandwidth for Streams on a Direct Rambus Memory. 80-89
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Kiyofumi Tanaka, Takashi Matsumoto, Kei Hiraki:
Lightweight Hardware Distributed Shared Memory Supported by Generalized Combining. 90-
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Instruction Scheduling & Speculation

Jian Huang, David J. Lilja:
Exploiting Basic Block Value Locality with Block Reuse. 106-114
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Eric Rotenberg, Quinn Jacobson, James E. Smith:
A Study of Control Independence in Superscalar Processors. 115-124
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Quinn Jacobson, James E. Smith:
Instruction Pre-Processing in Trace Processors. 125-129
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Marcio Merino Fernandes, Josep Llosa, Nigel P. Topham:
Distributed Modulo Scheduling. 130-134
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Ye Zhang, Lawrence Rauchwerger, Josep Torrellas:
Hardware for Speculative Parallelization of Partially-Parallel Loops in DSM Multiprocessors. 135-
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Cache Coherence

Maged M. Michael, Ashwini K. Nanda:
Design and Performance of Directory Caches for Scalable Shared Memory Multiprocessors. 142-151
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Ravi R. Iyer, Laxmi N. Bhuyan:
Switch Cache: A Framework for Improving the Remote Memory Access Latency of CC-NUMA Multiprocessors. 152-160
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Stefanos Kaxiras, James R. Goodman:
Improving CC-NUMA Performance Using Instruction-Based Prediction. 161-
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SMP Clusters

Erik Hagersten, Michael Koster:
WildFire: A Scalable Path for SMPs. 172-181
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Babak Falsafi, David A. Wood:
Parallel Dispatch Queue: A Queue-Based Programming Abstraction to Parallelize Fine-Grain Communication Protocols. 182-192
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Angelos Bilas, Dongming Jiang, Yuanyuan Zhou, Jaswinder Pal Singh:
Limits to the Performance of Software Shared Memory: A Layered Approach. 193-
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Cache and I/O Systems

Yiming Hu, Qing Yang, Tycho Nightingale:
RAPID-Cache - A Reliable and Inexpensive Write Cache for Disk I/O Systems. 204-213
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Thomas J. E. Schwarz, Jesse Steinberg, Walter A. Burkhard:
Permutation Development Data Layout (PDDL). 214-217
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Koji Inoue, Koji Kai, Kazuaki Murakami:
Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs. 218-222
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Yunseok Rhee, Joonwon Lee:
A Scalable Cache Coherent Scheme Exploiting Wormhole Routing Networks. 223-
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Communication Issues I

Marius Pirvu, Laxmi N. Bhuyan, Nan Ni:
The Impact of Link Arbitration on Switch Performance. 228-235
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Aniruddha S. Vaidya, Anand Sivasubramaniam, Chita R. Das:
LAPSES: A Recipe for High Performance Adaptive Router Design. 236-243
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Aske Plaat, Henri E. Bal, Rutger F. H. Hofman:
Sensitivity of Parallel Applications to Large Differences in Bandwidth and Latency in Two-Layer Interconnects. 244-
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Shared Memory

Sandhya Dwarkadas, Kourosh Gharachorloo, Leonidas I. Kontothanassis, Daniel J. Scales, Michael L. Scott, Robert Stets:
Comparative Evaluation of Fine- and Coarse-Grain Approaches for Software Distributed Shared Memory. 260-269
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Anne Condon, Mark D. Hill, Manoj Plakal, Daniel J. Sorin:
Using Lamport Clocks to Reason about Relaxed Memory Models. 270-278
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Alan L. Cox, Eyal de Lara, Y. Charlie Hu, Willy Zwaenepoel:
A Performance Comparison of Homeless and Home-Based Lazy Release Consistency Protocols in Software Shared Memory. 279-283
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Chen-Chi Kuo, John B. Carter, Ravindra Kuramkote:
MP-LOCKs: Replacing H/W Synchronization Primitives with Message Passing. 284-
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Communication Issues II

Yuanyuan Yang, Jianchao Wang:
Efficient All-to-All Broadcast in All-Port Mesh and Torus Networks. 290-299
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José Duato, Sudhakar Yalamanchili, Blanca Caminero, Damon S. Love, Francisco J. Quiles:
MMR: A High-Performance Multimedia Router - Architecture and Design Trade-Offs. 300-309
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Andrew Sohn, Yunheung Paek, Jui-Yuan Ku, Yuetsu Kodama, Yoshinori Yamaguchi:
Communication Studies of Single-Threaded and Multithreaded Distributed-Memory Multiprocessors. 310-314
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Juan Miguel Martínez, Pedro López, José Duato:
Impact of Buffer Size on the Efficiency of Deadlock Detection. 315-
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Workshop Overviews

David R. Kaeli, Bruce Jacobs:
Fifth Annual Workshop on Computer Education. 320
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Anand Sivasubramaniam, Mario Lauria:
Third Workshop on Communication, Architecture, and Applications for Network-Based Parallel Computing (CANPC '99). 320
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Dean M. Tullsen, Guang R. Gao:
Multithreaded Execution Architecture and Compilation. 321
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Jacques Chassin de Kergommeaux, Yves Denneulin, Thierry Gautier:
Parallel Computing for Irregular Applications. 321
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Russell M. Clapp, Ashwini K. Nanda, Josep Torrellas:
Second Workshop on Computer Architecture Evaluation Using Commercial Workloads. 322
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