Keijiro Nakamura

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1987

2 Keijiro Nakamura: Inverter-Minimum Networks. IEEE Trans. Computers 36(2): 226-230 (1987)

1979

1 Keijiro Nakamura: Synthesis of Gate-Minimum Multi-Output Two-Level Negative Gate Networks. IEEE Trans. Computers 28(10): 768-772 (1979)

1987
2		Keijiro Nakamura: Inverter-Minimum Networks. IEEE Trans. Computers 36(2): 226-230 (1987)
1979
1		Keijiro Nakamura: Synthesis of Gate-Minimum Multi-Output Two-Level Negative Gate Networks. IEEE Trans. Computers 28(10): 768-772 (1979)