En-Cheng Liu

2001
2	EE	Zhi-Hong Wang, En-Cheng Liu, Jianbang Lai, Ting-Chi Wang: Power minization in LUT-based FPGA technology mapping. ASP-DAC 2001: 635-640
1	EE	En-Cheng Liu, Ming-Shiun Lin, Jianbang Lai, Ting-Chi Wang: Slicing floorplan design with boundary-constrained modules. ISPD 2001: 124-129

Coauthor Index

1	Jianbang Lai	[1] [2]
2	Ming-Shiun Lin	[1]
3	Ting-Chi Wang	[1] [2]
4	Zhi-Hong Wang	[2]