| |
| 2005 | ||
|---|---|---|
| 4 | EE | Yuya Homma, Michitaka Kameyama, Yoshichika Fujioka, Nobuhiro Tomabechi: VLSI architecture based on packet data transfer scheme and its application. ISCAS (2) 2005: 1786-1789 |
| 2000 | ||
| 3 | EE | Yoshichika Fujioka, Nobuhiro Tomabechi: Design of a WSI scale parallel processor for intelligent robot control based on a dynamic reconfiguration of multi-operand arithmetic units. Systems and Computers in Japan 31(12): 33-42 (2000) |
| 1999 | ||
| 2 | EE | Yoshichika Fujioka, Michitaka Kameyama: Design of a reconfigurable VLSI processor for robot control based on bit-serial architecture. Systems and Computers in Japan 30(12): 43-51 (1999) |
| 1993 | ||
| 1 | Yoshichika Fujioka, Michitaka Kameyama: 2400-MFLOPS Reconfigurable Parallel VLSI Processor for Robot Control. ICRA (3) 1993: 149-154 | |
| 1 | Yuya Homma | [4] |
| 2 | Michitaka Kameyama | [1] [2] [4] |
| 3 | Nobuhiro Tomabechi | [3] [4] |