| |
| 2007 | ||
|---|---|---|
| 5 | EE | Hirokatsu Shirahama, Akira Mochizuki, Takahiro Hanyu, Masami Nakajima, Kazutami Arimoto: Design of a Processing Element Based on Quaternary Differential Logic for a Multi-Core SIMD Processor. ISMVL 2007: 43 |
| 2006 | ||
| 4 | EE | Toru Shimizu, Masami Nakajima, Masahiro Kainaga: Design and Evaluation of a Massively Parallel Processor Based on Matrix Architecture. IEICE Transactions 89-C(11): 1512-1518 (2006) |
| 1996 | ||
| 3 | EE | Masami Nakajima, Michitaka Kameyama: Design of Highly Parallel Linear Digital Circuits Based on Symbol-Level Redundancy. ISMVL 1996: 104-109 |
| 1994 | ||
| 2 | Masami Nakajima, Michitaka Kameyama: Design of Multiple-Valued Linear Digital Circuits for Highly Parallel k-Ary Operations. ISMVL 1994: 223-230 | |
| 1993 | ||
| 1 | Masami Nakajima, Michitaka Kameyama: Design of Multiple-Valued Linear Digital Circuits for Highly Parallel Unary Operations. ISMVL 1993: 283-288 | |
| 1 | Kazutami Arimoto | [5] |
| 2 | Takahiro Hanyu | [5] |
| 3 | Masahiro Kainaga | [4] |
| 4 | Michitaka Kameyama | [1] [2] [3] |
| 5 | Akira Mochizuki | [5] |
| 6 | Toru Shimizu | [4] |
| 7 | Hirokatsu Shirahama | [5] |