Tetsuro Nakamura

1994
2		Shoji Kawahito, Makoto Ishida, Tetsuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi: High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits. IEEE Trans. Computers 43(1): 34-42 (1994)
1992
1		Shoji Kawahito, Y. Mitsui, Makoto Ishida, Tetsuro Nakamura: Parallel Hardware Algorithms with Redundant Number Representations for Multiple-Valued Arithmetic VLSI. ISMVL 1992: 337-345

Coauthor Index

1	Tatsuo Higuchi	[2]
2	Makoto Ishida	[1] [2]
3	Michitaka Kameyama	[2]
4	Shoji Kawahito	[1] [2]
5	Y. Mitsui	[1]