| |
| 2005 | ||
|---|---|---|
| 2 | EE | Masanori Hariyama, Yasuhiro Kobayashi, Haruka Sasaki, Michitaka Kameyama: FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture. IEICE Transactions 88-A(12): 3516-3522 (2005) |
| 1 | EE | Masanori Hariyama, Haruka Sasaki, Michitaka Kameyama: Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access. IEICE Transactions 88-D(7): 1486-1491 (2005) |
| 1 | Masanori Hariyama | [1] [2] |
| 2 | Michitaka Kameyama | [1] [2] |
| 3 | Yasuhiro Kobayashi | [2] |