| |
| 1998 | ||
|---|---|---|
| 2 | EE | Takahiro Hanyu, Kaname Teranishi, Michitaka Kameyama: Multiple-Valued Floating-Gate-MOS Pass Logic and its Application to Logic-in-Memory VLSI. ISMVL 1998: 270-275 |
| 1 | EE | Takahiro Hanyu, Kaname Teranishi, Michitaka Kameyama: Design and evaluation of a digit-parallel multiple-valued content-addressable memory. Systems and Computers in Japan 29(11): 48-54 (1998) |
| 1 | Takahiro Hanyu | [1] [2] |
| 2 | Michitaka Kameyama | [1] [2] |