| |
| 2004 | ||
|---|---|---|
| 1 | EE | Frank K. Gürkaynak, Andreas Burg, Norbert Felber, Wolfgang Fichtner, D. Gasser, F. Hug, Hubert Kaeslin: A 2 Gb/s balanced AES crypto-chip implementation. ACM Great Lakes Symposium on VLSI 2004: 39-44 |
| 1 | Andreas Burg | [1] |
| 2 | Norbert Felber | [1] |
| 3 | Wolfgang Fichtner | [1] |
| 4 | D. Gasser | [1] |
| 5 | Frank K. Gürkaynak | [1] |
| 6 | Hubert Kaeslin | [1] |