2009 |
28 | EE | Arquimedes Canedo,
Ben A. Abderazek,
Masahiro Sowa:
Compiler Support for Code Size Reduction Using a Queue-Based Processor.
T. HiPEAC 2: 269-285 (2009) |
2008 |
27 | EE | Arquimedes Canedo,
Masahiro Sowa,
Ben A. Abderazek:
Quantitative Evaluation of Common Subexpression Elimination on Queue Machines.
ISPAN 2008: 25-30 |
26 | EE | Ben A. Abderazek,
Arquimedes Canedo,
Tsutomu Yoshinaga,
Masahiro Sowa:
The QC-2 parallel Queue processor architecture.
J. Parallel Distrib. Comput. 68(2): 235-245 (2008) |
25 | EE | Md. Musfiquzzaman Akanda,
Ben A. Abderazek,
Masahiro Sowa:
Dual-execution mode processor architecture.
The Journal of Supercomputing 44(2): 103-125 (2008) |
2007 |
24 | EE | Arquimedes Canedo,
Ben A. Abderazek,
Masahiro Sowa:
An Efficient Code Generation Algorithm for Code Size Reduction Using 1-Offset P-Code Queue Computation Model.
EUC 2007: 196-208 |
23 | EE | Ben A. Abderazek,
Mushfiquzzaman Akanda,
Tsutomu Yoshinaga,
Masahiro Sowa:
Mathematical Model for Multiobjective Synthesis of NoC Architectures.
ICPP Workshops 2007: 36 |
22 | EE | Arquimedes Canedo,
Ben A. Abderazek,
Masahiro Sowa:
New Code Generation Algorithm for QueueCoreAn Embedded Processor with High ILP.
PDCAT 2007: 185-192 |
21 | EE | Arquimedes Canedo,
Ben A. Abderazek,
Masahiro Sowa:
Queue Register File Optimization Algorithm for QueueCore Processor.
SBAC-PAD 2007: 169-176 |
20 | EE | Yuki Nakanishi,
Arquimedes Canedo,
Ben A. Abderazek,
Masahiro Sowa:
Optimizing Reaching Definitions Overhead in Queue Processors.
JCIT 2(4): 36-40 (2007) |
2006 |
19 | EE | Ben A. Abderazek,
Tsutomu Yoshinaga,
Masahiro Sowa:
Scalable Core-Based Methodology and Synthesizable Core for Systematic Design.
ICPP Workshops 2006: 345-352 |
18 | EE | Md. Musfiquzzaman Akanda,
Ben A. Abderazek,
Masahiro Sowa:
On the Design of a Dual-Execution Modes Processor: Architecture and Preliminary Evaluation.
ISPA Workshops 2006: 37-46 |
17 | EE | Ben A. Abderazek,
Sotaro Kawata,
Masahiro Sowa:
Design and architecture for an embedded 32-bit QueueCore.
J. Embedded Computing 2(2): 191-205 (2006) |
16 | EE | Ben A. Abderazek,
Tsutomu Yoshinaga,
Masahiro Sowa:
High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core.
The Journal of Supercomputing 38(1): 3-15 (2006) |
2005 |
15 | EE | Ben A. Abderazek,
Sotaro Kawata,
Tsutomu Yoshinaga,
Masahiro Sowa:
Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core.
EUC 2005: 340-349 |
14 | EE | Md. Musfiquzzaman Akanda,
Ben A. Abderazek,
Sotaro Kawata,
Masahiro Sowa:
An Efficient Dynamic Switching Mechanism (DSM) for Hybrid Processor Architecture.
EUC 2005: 77-86 |
13 | EE | Masahiro Sowa,
Ben A. Abderazek,
Tsutomu Yoshinaga:
Parallel Queue Processor Architecture Based on Produced Order Computation Model.
The Journal of Supercomputing 32(3): 217-229 (2005) |
2003 |
12 | EE | Ben A. Abderazek,
Soichi Shigeta,
Tsutomu Yoshinaga,
Masahiro Sowa:
On the Design of a Register Queue Based Processor Architecture (FaRM-rq).
ISPA 2003: 248-262 |
2002 |
11 | EE | Kirilka Nikolova,
Masahiro Sowa:
Compiler-Controlled Parallelism-Independent Scheduling Method for Cluster Computing Systems.
HPCS 2002: 182-189 |
10 | | Masahiro Sowa,
Ben A. Abderazek,
Soichi Shigeta,
Kirilka Nikolova,
Tsutomu Yoshinaga:
Proposal and Design of a Parallel Queue Processor Architecture (PQP).
IASTED PDCS 2002: 549-554 |
9 | EE | Kirilka Nikolova,
Sou Pei You,
Masahiro Sowa:
Compiler-Controlled Parallelism-Independent Scheduling for Parallel and Distributed Systems.
PARA 2002: 484-493 |
2001 |
8 | | Soichi Shigeta,
Kentaro Shimizu,
Masahiro Sowa:
Access route control by an extended key/lock scheme.
Comput. Syst. Sci. Eng. 16(5): 319-325 (2001) |
1997 |
7 | | Shusuke Okamoto,
Masahiro Sowa:
Intruction Fetch Mechanism for PN-Superscalar.
PDPTA 1997: 1406-1410 |
6 | | Mitsuaki Nakasumi,
Shusuke Okamoto,
Masahiro Sowa:
Program Controlled Cache Memory on Parallel Computer.
PDPTA 1997: 1423-1433 |
1996 |
5 | | Shusuke Okamoto,
Masahiro Sowa:
Hybrid Processor Based on VLIW and PN-Superscalar.
PDPTA 1996: 623-632 |
1994 |
4 | | Takaya Arita,
Hiromitsu Takagi,
Masahiro Sowa:
V++: An Instruction-Restructurable Processor Architecture.
HICSS (1) 1994: 398-408 |
1991 |
3 | EE | Takaya Arita,
Masahiro Sowa:
High Speed Synchronization for a Statically Scheduled Superscalar Processor.
International Journal of High Speed Computing 3(1): 77-87 (1991) |
1985 |
2 | | T. Smigelski,
Tadao Murata,
Masahiro Sowa:
A Timed Petri Net Model and Simulation of a Dataflow Computer.
PNPM 1985: 56-63 |
1982 |
1 | | Masahiro Sowa,
Tadao Murata:
A Data Flow Computer Architecture with Program and Token Memories.
IEEE Trans. Computers 31(9): 820-824 (1982) |