| 2003 |
|---|
| 10 | EE | Catherine H. Gebotys,
Robert J. Gebotys:
A Framework for Security on NoC Technologies.
ISVLSI 2003: 113-120 |
| 2002 |
|---|
| 9 | EE | Catherine H. Gebotys,
Robert J. Gebotys:
Secure Elliptic Curve Implementations: An Analysis of Resistance to Power-Attacks in a DSP Processor.
CHES 2002: 114-128 |
| 2000 |
|---|
| 8 | EE | Catherine H. Gebotys,
Robert J. Gebotys,
S. Wiratunga:
Power minimization derived from architectural-usage of VLIW processors.
DAC 2000: 308-311 |
| 1999 |
|---|
| 7 | EE | Catherine H. Gebotys,
Robert J. Gebotys:
Designing for Low Power in Complex Embedded DSP Systems.
HICSS 1999 |
| 1998 |
|---|
| 6 | EE | Catherine H. Gebotys,
Robert J. Gebotys:
Complexities in DSP Software Compilation: Performance, Code Size Power, Retargetability.
HICSS (3) 1998: 150-156 |
| 5 | EE | Catherine H. Gebotys,
Robert J. Gebotys:
An empirical comparison of algorithmic, instruction, and architectural power prediction models for high performance embedded DSP processors.
ISLPED 1998: 121-123 |
| 1997 |
|---|
| 4 | EE | Catherine H. Gebotys,
Robert J. Gebotys:
Performance-Power Optimization of Memory Components for Complex Embedded Systems.
HICSS (5) 1997: 152-159 |
| 1996 |
|---|
| 3 | EE | Catherine H. Gebotys,
Robert J. Gebotys:
Power Minimization in Heterogeneous Processing.
HICSS (1) 1996: 330-337 |
| 1995 |
|---|
| 2 | EE | Catherine H. Gebotys,
Robert J. Gebotys:
Optimized mapping of video applications to hardware-software for VLSI architectures.
HICSS (1) 1995: 41-48 |
| 1994 |
|---|
| 1 | | Catherine H. Gebotys,
Robert J. Gebotys:
Application-Specific Architectures for Field-Programmable VLSI Technologies.
HICSS (1) 1994: 124-131 |
