| |
| 2006 | ||
|---|---|---|
| 2 | EE | Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh, Yuan-Hua Chu: Design of STR level converters for SoCs using the multi-island dual-VDD design technique. ISCAS 2006 |
| 1995 | ||
| 1 | Hong-Yi Huang, Jinn-Shyan Wang, Yuan-Hua Chu, Tain-Shun Wu, Kuo-Hsing Cheng, Chung-Yu Wu: Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits. ISCAS 1995: 1572-1575 | |
| 1 | Yu-Juey Chang | [2] |
| 2 | Kuo-Hsing Cheng | [1] |
| 3 | Hong-Yi Huang | [1] |
| 4 | Jinn-Shyan Wang | [1] [2] |
| 5 | Chung-Yu Wu | [1] |
| 6 | Tain-Shun Wu | [1] |
| 7 | Chingwei Yeh (Ching-Wei Yeh) | [2] |