| 2007 |
|---|
| 11 | EE | Trieu-Kien Truong,
Chien-Chang Lin,
Shi-Huang Chen:
Segmentation of specific speech signals from multi-dialog environment using SVM and wavelet.
Pattern Recognition Letters 28(11): 1307-1313 (2007) |
| 2006 |
|---|
| 10 | EE | Jia-Wei Chen,
Chun-Hao Chang,
Chien-Chang Lin,
Yi-Huan Yang,
Jiun-In Guo,
Jinn-Shyan Wang:
A Condition-based Intra Prediction Algorithm for H.264/AVC.
ICME 2006: 1077-1080 |
| 9 | EE | Yao-Chang Yang,
Chien-Chang Lin,
Hsui-Cheng Chang,
Ching-Lung Su,
Jiun-In Guo:
A High Throughput VLSI Architecture Design for H.264 Context-Based Adaptive Binary Arithmetic Decoding with Look Ahead Parsing.
ICME 2006: 357-360 |
| 8 | EE | Tsung-Ching Lin,
Trieu-Kien Truong,
Shi-Huang Chen,
Chien-Chang Lin,
Pei-Ding Chen:
DCT-Based Image Codec Embedded Cubic Spline Interpolation with Optimal Quantization.
ISM 2006: 11-15 |
| 7 | EE | Chien-Chang Lin,
Shi-Huang Chen,
Tsung-Ching Lin,
Trieu-Kien Truong:
Feature Comparison among Various Wavelets in Speaker Recognition Using Support Vector Machine.
ISM 2006: 811-816 |
| 2005 |
|---|
| 6 | EE | Hsiu-Cheng Chang,
Chien-Chang Lin,
Jiun-In Guo:
A novel low-cost high-performance VLSI architecture for MPEG-4 AVC/H.264 CAVLC decoding.
ISCAS (6) 2005: 6110-6113 |
| 2004 |
|---|
| 5 | | Tai-Lun Chang,
Ying-Ming Tsai,
Chih-Da Chien,
Chien-Chang Lin,
Jiun-In Guo:
A high-performance MPEG4 bitstream processing core.
ICME 2004: 467-470 |
| 4 | EE | Chih-Da Chien,
Chien-Chang Lin,
Jiun-In Guo,
Tien-Fu Chen:
A power-aware IP core generator for the one-dimensional discrete Fourier transform.
ISCAS (3) 2004: 637-640 |
| 2003 |
|---|
| 3 | EE | Jiun-In Guo,
Chih-Da Chien,
Chien-Chang Lin:
A parameterized low power design for the variable-length discrete Fourier transform using dynamic pipelining.
ISCAS (5) 2003: 293-296 |
| 2002 |
|---|
| 2 | EE | Jiun-In Guo,
Chien-Chang Lin:
A new hardware efficient design for the one dimensional discrete Fourier transform.
ISCAS (5) 2002: 549-552 |
| 1 | EE | Jiun-In Guo,
Chien-Chang Lin,
Chih-Da Chien:
A Low-Power Parameterized Hardware Design for the One-Dimensional Discrete Fourier Transform of Variable Lengths.
Journal of Circuits, Systems, and Computers 11(4): 405-428 (2002) |
