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Pablo Viana

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2008
7EEPablo Viana, Ann Gordon-Ross, Edna Barros, Frank Vahid: A table-based method for single-pass cache optimization. ACM Great Lakes Symposium on VLSI 2008: 71-76
2007
6EEAnn Gordon-Ross, Pablo Viana, Frank Vahid, Walid A. Najjar, Edna Barros: A one-shot configurable-cache tuner for improved energy and performance. DATE 2007: 755-760
5EEAndre Silva, Guilherme Esmeraldo, Edna Barros, Pablo Viana: Cache-Analyzer: Design Space Evaluation of Configurable-Caches in a Single-Pass. IEEE International Workshop on Rapid System Prototyping 2007: 3-9
2006
4EEPablo Viana, Ann Gordon-Ross, Eamonn J. Keogh, Edna Barros, Frank Vahid: Configurable cache subsetting for fast cache tuning. DAC 2006: 695-700
3EEAbel Guilhermino S. Filho, Pablo Viana, Edna Barros, Manoel Eusebio de Lima: Tuning Mechanism for Two-Level Cache Hierarchy Intended for Instruction Caches and Low Energy Consumption. SBAC-PAD 2006: 125-132
2004
2EEPablo Viana, Edna Barros, Sandro Rigo, Rodolfo Azevedo, Guido Araujo: Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology. DATE 2004: 734-735
2003
1EEPablo Viana, Edna Barros, Sandro Rigo, Rodolfo Azevedo, Guido Araujo: Exploring Memory Hierarchy with ArchC. SBAC-PAD 2003: 2-9

Coauthor Index

1Guido Araujo [1] [2]
2Rodolfo Azevedo [1] [2]
3Edna Barros [1] [2] [3] [4] [5] [6] [7]
4Guilherme Esmeraldo [5]
5Abel Guilhermino S. Filho [3]
6Ann Gordon-Ross [4] [6] [7]
7Eamonn J. Keogh [4]
8Manoel Eusebio de Lima [3]
9Walid A. Najjar [6]
10Sandro Rigo [1] [2]
11Andre Silva [5]
12Frank Vahid [4] [6] [7]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)